Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
application markets
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
the references to Nexperia, as shown below.
Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,
use http://www.nexperia.com
Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use
salesaddresses@nexperia.com (email)
Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
the version, as shown below:
- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
Should be replaced with:
- © Nexperia B.V. (year). All rights reserved.
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail
or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and
understanding,
Kind regards,
Team Nexperia
1. General description
The 74HC10-Q100; 74HCT10-Q100 is a triple 3-input NAND gate. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of V
CC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Complies with JEDEC standard JESD7A
Input levels:
For 74HC10-Q100: CMOS level
For 74HCT10-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Ordering information
74HC10-Q100; 74HCT10-Q100
Triple 3-input NAND gate
Rev. 1 — 21 February 2013 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC10D-Q100 40 C to +125 C SO14 plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74HCT10D-Q100
74HC10PW-Q100 40 C to +125 C TSSOP14 plastic thin shrink small outline package;
14 leads; body width 4.4 mm
SOT402-1
74HCT10PW-Q100
74HC_HCT10_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 21 February 2013 2 of 13
NXP Semiconductors
74HC10-Q100; 74HCT10-Q100
Triple 3-input NAND gate
4. Functional diagram
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram for one gate
mna757
3Y
3C
11
3B
10
3A
9
2C
5
2B
4
2A
3
1C
13
1B
2
1A
1
8
2Y
6
1Y
12
mna759
12
&
&
&
6
8
13
2
1
5
4
3
11
10
9
mna758
A
B
C
Y
Fig 4. Pin configuration SO14 Fig 5. Pin configuration TSSOP14
+&4
+&74
$ 9
&&
% &
$ <
% &
& %
< $
*1' <
DDD





+&74
$
%
$
%
&
<





Table 2. Pin description
Symbol Pin Description
1A, 2A, 3A 1, 3, 9 data input
1B, 2B, 3B 2, 4, 10 data input
GND 7 ground (0 V)
1C, 2C, 3C 13, 5, 11 data input
1Y, 2Y, 3Y 12, 6, 8 data output
V
CC
14 supply voltage

74HCT10D-Q100J

Mfr. #:
Manufacturer:
Nexperia
Description:
Logic Gates 74HCT10D-Q100/SO14/REEL 13" Q1
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union