74HC_HCT10_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 21 February 2013 6 of 13
NXP Semiconductors
74HC10-Q100; 74HCT10-Q100
Triple 3-input NAND gate
[1] t
pd
is the same as t
PHL
and t
PLH
.
[2] t
t
is the same as t
THL
and t
TLH
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in W):
P
D
=C
PD
V
CC
2
f
i
N+ (C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of outputs.
11. Waveform and test circuit
74HCT10-Q100
t
pd
propagation delay nA, nB to nY; see Figure 6
[1]
V
CC
= 4.5 V - 14 24 30 36 ns
V
CC
= 5.0 V; C
L
=15pF - 11 - - - ns
t
t
transition time V
CC
= 4.5 V; see Figure 6
[2]
- 7 15 19 22 ns
C
PD
power dissipation
capacitance
per package;
V
I
=GNDtoV
CC
1.5 V
[3]
-14- - -pF
Table 7. Dynamic characteristics
GND = 0 V; C
L
= 50 pF; for test circuit see Figure 7.
Symbol Parameter Conditions 25 C 40 C to +125 C Unit
Min Typ Max Max
(85 C)
Max
(125 C)
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 6. Input to output propagation delays
Q%Q&LQSXW
*1'
O
9
0
9
0
9
;
9
<
9
2+
9
2/
W
7+/
W
7/+
W
3+/
W
3/+
Q<RXWSXW
Table 8. Measurement points
Type Input Output
V
M
V
M
V
X
V
Y
74HC10-Q100 0.5V
CC
0.5V
CC
0.1V
CC
0.9V
CC
74HCT10-Q100 1.3 V 1.3 V 0.1V
CC
0.9V
CC
