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LTC1435AIG#TRPBF

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13
LTC1435A
APPLICATIONS INFORMATION
WUU
U
on and off again. It is determined by internal timing delays
and the gate charge required to turn on the top MOSFET.
Low duty cycle applications may approach this minimum
on-time limit. If the duty cycle falls below what can be
accommodated by the minimum on-time, the LTC1435A
will begin to skip cycles. The output voltage will continue
to be regulated, but the ripple current and ripple voltage will
increase. Therefore this limit should be avoided.
The minimum on-time for the LTC1435A in a properly
configured application is less than 300ns but increases at
low ripple current amplitudes (see Figure 7). If an appli-
cation is expected to operate close to the minimum on-time
limit, an inductor value must be chosen that is low enough
to provide sufficient ripple amplitude to meet the minimum
on-time requirement. To determine the proper value, use
the following procedure:
1. Calculate on-time at maximum supply, t
ON(MIN)
=
(1/f)(V
OUT
/V
IN(MAX)
).
2. Use Figure 7 to obtain the peak-to-peak inductor ripple
current as a percentage of I
MAX
necessary to achieve the
calculated t
ON(MIN)
.
3. Ripple amplitude ∆I
L(MIN)
= (% from Figure 7)(I
MAX
)
where I
MAX
= 0.1/R
SENSE
.
4. L
MAX
=
t
VV
I
ON MIN
IN MAX OUT
L MIN
()
()
()
–
∆
Choose an inductor less than or equal to the calculated L
MAX
to ensure proper operation.
Because of the sensitivity of the LTC1435A current com-
parator when operating close to the minimum on-time limit,
it is important to prevent stray magnetic flux generated by
the inductor from inducing noise on the current sense re-
sistor, which may occur when axial type cores are used. By
orienting the sense resistor on the radial axis of the induc-
tor (see Figure 8), this noise will be minimized.
Figure 7. Minimum On-Time vs Inductor Ripple Current
INDUCTOR RIPPLE CURRENT (% OF I
MAX
)
0
200
MINIMUM ON-TIME (ns)
250
300
350
400
RECOMMENDED
REGION FOR MIN
ON-TIME AND
MAX EFFICIENCY
10 20 30 40
1435A F07
50 60 70
L
INDUCTOR
1435A F08
Figure 8. Allowable Inductor/R
SENSE
Layout Orientations
Efficiency Considerations
The efficiency of a switching regulator is equal to the out-
put power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce the
most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1435A circuits. LTC1435A V
IN
current, INTV
CC
current, I
2
R losses, and topside MOSFET transition losses.
1. The V
IN
current is the DC supply current given in the
electrical characteristics which excludes MOSFET driver
and control currents. V
IN
current results in a small
(< 1%) loss which increases with V
IN
.
2. INTV
CC
current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high
to low again, a packet of charge dQ moves from INTV
CC
to ground. The resulting dQ/dt is a current out of INTV
CC
that is typically much larger than the control circuit cur-
rent. In continuous mode, I
GATECHG
= f(Q
T
+ Q
B
), where
Q
T
and Q
B
are the gate charges of the topside and bot-
tom side MOSFETs.
14
LTC1435A
APPLICATIONS INFORMATION
WUU
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By powering EXTV
CC
from an output-derived source, the
additional V
IN
current resulting from the driver and
control currents will be scaled by a factor of
Duty Cycle/Efficiency. For example, in a 20V to 5V ap-
plication, 10mA of INTV
CC
current results in approxi-
mately 3mA of V
IN
current. This reduces the midcurrent
loss from 10% or more (if the driver was powered di-
rectly from V
IN
) to only a few percent.
3. I
2
R losses are predicted from the DC resistances of the
MOSFET, inductor and current shunt. In continuous
mode the average output current flows through L and
R
SENSE
, but is “chopped” between the topside main
MOSFET and the synchronous MOSFET. If the two
MOSFETs have approximately the same R
DS(ON)
, then
the resistance of one MOSFET can simply be summed
with the resistances of L and R
SENSE
to obtain I
2
R
losses. For example, if each R
DS(ON)
= 0.05Ω,
R
L
= 0.15Ω, and R
SENSE
= 0.05Ω, then the total resis-
tance is 0.25Ω. This results in losses ranging from 3%
to 10% as the output current increases from 0.5A to
2A. I
2
R losses cause the efficiency to drop at high output
currents.
4. Transition losses apply only to the topside MOSFET(s),
and only when operating at high input voltages (typically
20V or greater). Transition losses can be estimated from:
Transition Loss = 2.5 (V
IN
)
1.85
(I
MAX
)(C
RSS
)(f)
Other losses, including C
IN
and C
OUT
ESR dissipative
losses, Schottky conduction losses during dead-time,
and inductor core losses, generally account for less than
2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take sev-
eral cycles to respond to a step in DC (resistive) load cur-
rent. When a load step occurs, V
OUT
immediately shifts by
an amount equal to (∆I
LOAD
)(ESR), where ESR is the ef-
fective series resistance of C
OUT
. ∆I
LOAD
also begins to
charge or discharge C
OUT
which generates a feedback error
signal. The regulator loop then acts to return V
OUT
to its
steady-state value. During this recovery time V
OUT
can be
monitored for overshoot or ringing, which would indicate
a stability problem. The I
TH
external components shown in
the Figure 1 circuit will provide adequate compensation for
most applications.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(C
LOAD
).
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
Automotive Considerations:
Plugging into the Cigarette Lighter
As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during operation.
But before you connect, be advised: you are plugging into
the supply from hell. The main battery line in an automo-
bile is the source of a number of nasty potential transients,
including load dump, reverse battery and double battery.
Load dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alternator
can cause a positive spike as high as 60V which takes several
hundred milliseconds to decay. Reverse battery is just what
it says, while double battery is a consequence of tow truck
operators finding that a 24V jump start cranks cold engines
faster than 12V.
The network shown in Figure 9 is the most straightforward
approach to protect a DC/DC converter from the ravages
of an automotive battery line. The series diode prevents
current from flowing during reverse battery, while the
transient suppressor clamps the input voltage during load
dump. Note that the transient suppressor should not
Figure 9. Automotive Application Protection
1435A F09
50A I
PK
RATING
LTC1435A
TRANSIENT VOLTAGE
SUPPRESSOR
GENERAL INSTRUMENT
1.5KA24A
V
IN
12V
15
LTC1435A
APPLICATIONS INFORMATION
WUU
U
conduct during double battery operation, but must still
clamp the input voltage below breakdown of the converter.
Although the LTC1435A has a maximum input voltage of
36V, most applications will be limited to 30V by the
MOSFET BV
DSS
.
Design Example
As a design example, assume V
IN
= 12V(nominal), V
IN
=
22V(max), V
OUT
= 1.6V, I
MAX
= 3A and f = 250kHz, R
SENSE
and C
OSC
can immediately be calculated:
R
SENSE
= 100mV/3A = 0.033Ω
C
OSC
= 1.37(10
4
)/250 – 11 = 43pF
Referring to Figure 3, a 4.7µH inductor falls within the rec-
ommended range. To check the actual value of the ripple
current the following equation is used:
∆I
V
fL
V
V
L
OUT OUT
IN
=
()()
1–
The highest value of the ripple current occurs at the maxi-
mum input voltage:
∆I
V
kHz H
V
V
L
=
µ
()
=
16
250 4 7
1
16
22
13
.
.
–
.
.A
The lowest duty cycle also occurs at maximum input volt-
age. The on-time during this condition should be checked
to make sure it doesn’t violate the LTC1435A’s minimum
on-time and cause cycle skipping to occur. The required on-
time at V
IN(MAX)
is:
t
V
Vf
V
V kHz
ns
ON MIN
OUT
IN MAX
()
()
.
=
()()
=
()( )
=
16
22 250
291
The ∆I
L
was previously calculated to be 1.3A, which is 43%
of I
MAX
. From Figure 7, the LTC1435A minimum on-time
at 43% ripple is about 235ns. Therefore, the minimum on-
time is sufficient and no cycle skipping will occur.
The power dissipation on the topside MOSFET can be easily
estimated. Choosing a Siliconix Si4412DY results in:
R
DS(ON)
= 0.042Ω, C
RSS
= 100pF. At maximum input volt-
age with T(estimated) = 50°C:
P
V
V
CC
V A pF kHz mW
MAIN
=
()
+
()
°− °
()
[]
()
+
()()( )( )
=
16
22
3 1 0 005 50 25 0 042
2 5 22 3 100 250 88
2
185
.
..
.
.
Ω
The most stringent requirement for the synchronous
N-channel MOSFET occurs when V
OUT
= 0 (i.e. short cir-
cuit). In this case the worst-case dissipation rises to:
PI R
SYNC SC AVG DS ON
=
()
+
()
() ()
2
1
δ
With the 0.033Ω sense resistor I
SC(AVG)
= 4A will result,
increasing the Si4412DY dissipation to 950mW at a die tem-
perature of 105°C.
C
IN
is chosen for an RMS current rating of at least 1.5A at
temperature. C
OUT
is chosen with an ESR of 0.03Ω for low
output ripple. The output ripple in continuous mode will be
highest at the maximum input voltage. The output voltage
ripple due to ESR is approximately:
V
ORIPPLE
= R
ESR
(∆I
L
) = 0.03Ω(1.3A) = 39mV
P-P
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1435A. These items are also illustrated graphically in
the layout diagram of Figure 10. Check the following in your
layout:
1. Are the signal and power grounds segregated? The
LTC1435A signal ground pin must return to the (–) plate
of C
OUT
. The power ground connects to the source of the
bottom N-channel MOSFET, anode of the Schottky di-
ode, and (–) plate of C
IN
, which should have as short lead
lengths as possible.
2. Does the V
OSENSE
pin connect directly to the feedback
resistors? The resistive divider R1, R2 must be con-
nected between the (+) plate of C
OUT
and signal ground.
The 100pF capacitor should be as close as possible to
the LTC1435A.
3. Are the SENSE
–
and SENSE
+
leads routed together with
minimum PC trace spacing? The filter capacitor between
SENSE
+
and SENSE
–
should be as close as possible to
the LTC1435A.
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LTC1435AIG#TRPBF

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Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Single Const Freq Syn Sw Reg Cntrl
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