ICS527-03
CLOCK SLICER USER CONFIGURABLE PECL OUTPUT ZDB PECL ZDB AND MULTIPLIER/DIVIDER
IDT™ / ICS™
CLOCK SLICER USER CONFIGURABLE PECL OUTPUT ZDB 3
ICS527-03 REV E 051310
External Components
Decoupling Capacitors
As with any high performance mixed-signal IC, the
ICS527-03 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. They
must be connected close to the device to minimize lead
inductance.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
Determining (setting) the ICS527-03
Dividers
The user has full control in setting the desired output
clock over the range shown in the table on page 2. The
user should connect the divider select input pins directly
to ground (or VDD, although this is not required
because of internal pull-ups) during Printed Circuit
Board layout, so the ICS527-03 automatically produces
the correct clock when all components are soldered. It
is also possible to connect the inputs to parallel I/O
ports in order to switch frequencies.
The output of the ICS527-03 can be determined by the
following simple equation:
Where:
Reference Divider Word (RDW) = 0 to 127
Feedback Divider Word (FDW) = 0 to 127
FB Frequency is the same as either CLK1 or
CLK2 depending on feedback connection
Also, the following operating ranges should be
observed:
The output divide should be selected depending on
the frequency of CLK1. The table on page 2 gives
the ranges.
The dividers are expressed as integers. For example, if
a 50 MHz output on CLK1 is desired from a 40 MHz
input, the reference divider word (RDW) should be 2
and the feedback divider word (FDW) should be 3 which
gives the required 5/4 multiplication. If multiple choices
of dividers are available, then the lowest numbers
should be used. In this example, the output divide (OD)
should be selected to be 2. Then R6:R0 is 0000010,
F6:F0 is 0000011 and S1:S0 is 00. Also, this example
assumes CLK1 is connected to FBIN.
If you need assistance determining the optimum divider
settings, please send an e-mail to ics-mk@icst.com
with the desired input clock and the desired output
frequency.
FB Frequency
Input Frequency
FDW 2+
RDW 2+
------------------------
×=
300kHz
Input Frequency
RDW 2+
-------------------------------------------
20 MHz<<
