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XC2C64A-7VQ44I

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
XC2C64A CoolRunner-II CPLD
4 www.xilinx.com DS311 (v2.3) November 19, 2008
Product Specification
R
LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications
LVCMOS 2.5V DC Voltage Specifications
LVCMOS 1.8V DC Voltage Specifications
Symbol Parameter Test Conditions Min. Max. Units
V
CCIO
Input source voltage 3.0 3.6 V
V
IH
High level input voltage 2 3.9 V
V
IL
Low level input voltage –0.3 0.8 V
V
OH
High level output voltage I
OH
= –8 mA, V
CCIO
= 3V V
CCIO
– 0.4V - V
I
OH
= –0.1 mA, V
CCIO
= 3V V
CCIO
– 0.2V - V
V
OL
Low level output voltage I
OL
= 8 mA, V
CCIO
= 3V - 0.4 V
I
OL
= 0.1 mA, V
CCIO
= 3V - 0.2 V
Symbol Parameter Test Conditions Min. Max. Units
V
CCIO
Input source voltage 2.3 2.7 V
V
IH
High level input voltage 1.7 V
CCIO
+ 0.3
(1)
V
V
IL
Low level input voltage –0.3 0.7 V
V
OH
High level output voltage I
OH
= –8 mA, V
CCIO
= 2.3V V
CCIO
– 0.4V - V
I
OH
= –0.1 mA, V
CCIO
= 2.3V V
CCIO
– 0.2V - V
V
OL
Low level output voltage I
OL
= 8 mA, V
CCIO
= 2.3V - 0.4 V
I
OL
= 0.1 mA, V
CCIO
= 2.3V - 0.2 V
1. The VIH Max value represents the JEDEC specification for LVCMOS25. The CoolRunner-II CPLD input buffer can tolerate up to 3.9V
without physical damage.
Symbol Parameter Test Conditions Min. Max. Units
V
CCIO
Input source voltage - 1.7 1.9 V
V
IH
High level input voltage - 0.65 x V
CCIO
V
CCIO
+ 0.3
(1)
V
V
IL
Low level input voltage - –0.3 0.35 x V
CCIO
V
V
OH
High level output voltage I
OH
= –8 mA, V
CCIO
= 1.7V V
CCIO
– 0.45 - V
I
OH
= –0.1 mA, V
CCIO
= 1.7V V
CCIO
– 0.2 - V
V
OL
Low level output voltage I
OL
= 8 mA, V
CCIO
= 1.7V - 0.45 V
I
OL
= 0.1 mA, V
CCIO
= 1.7V - 0.2 V
1. The V
IH
Max value represents the JEDEC specification for LVCMOS18. The CoolRunner-II CPLD input buffer can tolerate up to 3.9V
without physical damage.
XC2C64A CoolRunner-II CPLD
DS311 (v2.3) November 19, 2008 www.xilinx.com 5
Product Specification
R
LVCM OS 1.5V DC Voltage Specifications
Schmitt Trigger Input DC Voltage Specifications
Symbol Parameter
(1)
Test Conditions Min. Max. Units
V
CCIO
Input source voltage - 1.4 1.6 V
V
T+
Input hysteresis threshold voltage - 0.5 x V
CCIO
0.8 x V
CCIO
V
V
T-
-0.2 x V
CCIO
0.5 x V
CCIO
V
V
OH
High level output voltage I
OH
= –8 mA, V
CCIO
= 1.4V V
CCIO
– 0.45 - V
I
OH
= –0.1 mA, V
CCIO
= 1.4V V
CCIO
– 0.2 - V
V
OL
Low level output voltage I
OL
= 8 mA, V
CCIO
= 1.4V - 0.4 V
I
OL
= 0.1 mA, V
CCIO
= 1.4V - 0.2 V
Notes:
1. Hysteresis used on 1.5V inputs.
Symbol Parameter Test Conditions Min. Max. Units
V
CCIO
Input source voltage - 1.4 3.9 V
V
T+
Input hysteresis threshold voltage - 0.5 x V
CCIO
0.8 x V
CCIO
V
V
T-
-0.2 x V
CCIO
0.5 x V
CCIO
V
XC2C64A CoolRunner-II CPLD
6 www.xilinx.com DS311 (v2.3) November 19, 2008
Product Specification
R
AC Electrical Characteristics Over Recommended Operating Conditions
Symbol Parameter
-5 -7
UnitsMin. Max. Min. Max.
T
PD1
Propagation delay single p-term - 4.6 - 6.7 ns
T
PD2
Propagation delay OR array - 5.0 - 7.5 ns
T
SUD
Direct input register clock setup time 2.4 - 3.3 - ns
T
SU1
Setup time (single p-term) 2.0 - 2.5 - ns
T
SU2
Setup time (OR array) 2.4 - 3.3 - ns
T
HD
Direct input register hold time 0 - 0 - ns
T
H
P-term hold time 0 - 0 - ns
T
CO
Clock to output - 3.9 - 6.0 ns
F
TOGGLE
(1)
Internal toggle rate
(1)
-500-300MHz
F
SYSTEM1
(2)
Maximum system frequency
(2)
-263-159MHz
F
SYSTEM2
(2)
Maximum system frequency
(2)
-238-141MHz
F
EXT1
(3)
Maximum external frequency
(3)
-169-118MHz
F
EXT2
(3)
Maximum external frequency
(3)
-159-108MHz
T
PSUD
Direct input register p-term clock setup time 0.9 - 1.7 - ns
T
PSU1
P-term clock setup time (single p-term) 0.6 - 0.9 - ns
T
PSU2
P-term clock setup time (OR array) 1.0 - 1.7 - ns
T
PHD
Direct input register p-term clock hold time 1.3 - 1.4 - ns
T
PH
P-term clock hold 1.5 - 1.7 - ns
T
PCO
P-term clock to output - 6.0 - 8.4 ns
T
OE
/T
OD
Global OE to output enable/disable - 8.0 - 10.0 ns
T
POE
/T
POD
P-term OE to output enable/disable - 9.0 - 11.0 ns
T
MOE
/T
MOD
Macrocell driven OE to output enable/disable - 9.0 - 11.0 ns
T
PAO
P-term set/reset to output valid - 7.3 - 9.7 ns
T
AO
Global set/reset to output valid - 6.0 - 8.3 ns
T
SUEC
Register clock enable setup time 3.0 - 3.7 - ns
T
HEC
Register clock enable hold time 0 - 0 - ns
T
CW
Global clock pulse width High or Low 1.4 - 2.2 - ns
T
PCW
P-term pulse width High or Low 5.0 - 7.5 - ns
T
APRPW
Asynchronous preset/reset pulse width (High or Low) 5.0 - 7.5 - ns
T
CONFIG
(4)
Configuration time - 50.0 - 50.0 μs
Notes:
1. F
TOGGLE
is the maximum frequency of a dual edge triggered T flip-flop with output enabled.
2. F
SYSTEM
(1/T
CYCLE
) is the internal operating frequency for a device fully populated with 16-bit up/down, Resetable binary counter
(one counter per function block).
3. F
EXT
(1/T
SU1
+T
CO
) is the maximum external frequency.
4. Typical configuration current during
T
CONFIG
is 2.3 mA.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

XC2C64A-7VQ44I

Mfr. #:
Buy XC2C64A-7VQ44I
Manufacturer:
Xilinx
Description:
CPLD - Complex Programmable Logic Devices XC2C64A-7VQ44I
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New from this manufacturer.
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