RT8064
10
DS8064-07 November 2012www.richtek.com
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Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current, ΔI
L
, increases with higher V
IN
and decreases
with higher inductance.
⎛⎞
Δ×
⎜⎟
⎝⎠
OUT OUT
L
IN
VV
I = 1
f x L V
Having a lower ripple current reduces not only the ESR
losses in the output capacitors but also the output voltage
ripple. Highest efficiency operation is achieved by reducing
ripple current at low frequency, but attaining this goal
requires a large inductor.
For the ripple current selection, the value of
ΔI
L
= 0.4 (I
MAX
)
is a reasonable starting point. The largest ripple current
occurs at the highest V
IN
. To guarantee that the ripple
current stays below a specified maximum value, the
inductor value needs to be chosen according to the following
equation :
⎡⎤⎡⎤
×−
⎢⎥⎢⎥
Δ
⎣⎦⎣⎦
OUT OUT
L(MAX) IN(MAX)
VV
L = 1
f x I V
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
input. At best, this ringing can couple to the output and
be mistaken as loop instability. At worst, a sudden inrush
of current through the long wires can potentially cause a
voltage spike at V
IN
large enough to damage the part.
Slope Compensation and Peak Inductor Current
Slope compensation provides stability in constant
frequency architectures by preventing sub-harmonic
oscillations at duty cycles greater than 50%. It is
accomplished internally by adding a compensating ramp
to the inductor current signal. Normally, the peak inductor
current is reduced when slope compensation is added.
For the IC, however, separated inductor current signal is
used to monitor over current condition, so the maximum
output current stays relatively constant regardless of the
duty cycle.
Hiccup Mode Under Voltage Protection
A Hiccup Mode Under Voltage Protection (UVP) function
is provided for the IC. When the FB voltage drops below
half of the feedback reference voltage, V
FB
, the UVP
function is triggered to auto soft-start the power stage
until this event is cleared. The Hiccup Mode UVP reduces
the input current in short circuit conditions, but will not be
triggered during soft-start process.
Under Voltage Lockout Threshold
The RT8064 includes an input under voltage lockout
protection (UVLO) function. If the input voltage exceeds
the UVLO rising threshold voltage, the converter will reset
and prepare the PWM for operation. However, if the input
voltage falls below the UVLO falling threshold voltage during
normal operation, the device will stop switching. The UVLO
rising and falling threshold voltage has a hysteresis to
prevent noise caused reset.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
Figure 2. Switching Frequency vs. RT Resistor
Ω
0.0
0.4
0.8
1.2
1.6
2.0
2.4
0 300 600 900 1200 1500 1800 2100
R
RT
(k )
Switching Frequency (MHz) 1
RT8064
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Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Figure 3. Derating Curve of Maximum Power Dissipation
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of the IC.
` Connect the terminal of the input capacitor (s), C
IN
, as
close to the VIN pin as possible. This capacitor provides
the AC current into the internal power MOSFETs.
` LX node experiences high frequency voltage swings so
should be kept within a small area.
` Keep all sensitive small signal nodes away from the LX
node to prevent stray capacitive noise pick up.
` Connect the FB pin directly to the feedback resistors.
The resistive voltage divider must be connected between
V
OUT
and GND.
Figure 4. PCB Layout Guide
COMP
SS
EN
VIN
PGOOD
FB
LX
RT
GND
2
3
4
5
6
7
8
9
Place the compensation
components as close to
the IC as possible
V
OUT
GND
R2
R1
V
IN
C
IN
C
OUT
V
OUT
L1
R
COMP
C
COMP
LX should be connected
to inductor by wide and
short trace, and keep
sensitive components
away from this trace
Place the feedback
resistors as close to
the IC as possible
Place the input and output capacitors
as close to the IC as possible
GND
R
OSC
GND
C
SS
Place the compensation
components as close to
the IC as possible
V
OUT
GND
R2
R1
V
IN
C
IN
C
OUT
V
OUT
L1
R
COMP
C
COMP
LX should be connected
to inductor by wide and
short trace, and keep
sensitive components
away from this trace
Place the feedback
resistors as close to
the IC as possible
Place the input and output capacitors
as close to the IC as possible
GND
R
OSC
COMP
SS
VIN
PGOOD
FB
RT
LX
EN
7
6
5
1
2
3
4
8
GND
9
GND
C
SS
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
0 25 50 75 100 125
Ambient Temperature (°C)
Maximum Power Dissipation (W) 1
Four-Layer PCB
SOP-8 (Exposed Pad)
WDFN-8L 3x3
maximum power dissipation can be calculated by the
following formula :
P
D(MAX)
= (T
J(MAX)
T
A
) / θ
JA
where T
J(MAX)
is the maximum junction temperature, T
A
is
the ambient temperature, and θ
JA
is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θ
JA
, is layout dependent. For
SOP-8 (Exposed Pad) packages, the thermal resistance,
θ
JA
, is 75°C/W on a standard JEDEC 51-7 four-layer
thermal test board. For WDFN-8L 3x3 packages, the
thermal resistance, θ
JA
, is 70°C/W on a standard JEDEC
51-7 four-layer thermal test board. The maximum power
dissipation at T
A
= 25°C can be calculated by the following
formulas :
P
D(MAX)
= (125°C 25°C) / (75°C/W) = 1.333W for
SOP-8 (Exposed Pad) package
P
D(MAX)
= (125°C 25°C) / (70°C/W) = 1.429W for
WDFN-8L 3x3 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance, θ
JA
. The derating curves in Figure 3 allow the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
RT8064
12
DS8064-07 November 2012www.richtek.com
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Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Outline Dimension
A
B
J
F
H
M
C
D
I
Y
X
EXPOSED THERMAL PAD
(Bottom of Package)
8-Lead SOP (Exposed Pad) Plastic Package
Dimensions In Millimeters Dimensions In Inches
Symbol
Min Max Min Max
A 4.801 5.004 0.189 0.197
B 3.810 4.000 0.150 0.157
C 1.346 1.753 0.053 0.069
D 0.330 0.510 0.013 0.020
F 1.194 1.346 0.047 0.053
H 0.170 0.254 0.007 0.010
I 0.000 0.152 0.000 0.006
J 5.791 6.200 0.228 0.244
M 0.406 1.270 0.016 0.050
X 2.000 2.300 0.079 0.091
Option 1
Y 2.000 2.300 0.079 0.091
X 2.100 2.500 0.083 0.098
Option 2
Y 3.000 3.500 0.118 0.138

RT8064ZQW

Mfr. #:
Manufacturer:
Description:
IC REG BUCK ADJUSTABLE 2A 8WDFN
Lifecycle:
New from this manufacturer.
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