M41T00M6F Datasheet M41T00M6F, M41T00M6E | P13-P15

DocID6100 Rev 10 13/25

M41T00 Device operation

Table 4. RTC power down/up trip points dc characteristics

Symbol

Parameter

(1)(2)

1. Valid for ambient operating temperature: T

= –40 to 85 °C; V

= 2.0 to 5.5 V (except where otherwise

noted).

2. All voltages referenced to V

Min Typ

Max

(3)

3. In 3.3 V application, if initial battery voltage is > 3.4 V, it may be necessary to reduce battery voltage (i.e.,

through wave soldering the battery) in order to avoid inadvertent switchover/deselection for V

-10 %

operation.

Unit

(4)

4. Switchover and deselect point.

Backup switchover voltage

BAT

-0.80 V

BAT

-0.50 V

BAT

-0.30

M41T00 clock operation M41T00

14/25 DocID6100 Rev 10

3 M41T00 clock operation

The eight byte clock register (see Table 5) is used to both set the clock and to read the date

and time from the clock, in a binary coded decimal format. Seconds, minutes, and hours are

contained within the first three registers. Bits D6 and D7 of clock register 2 (century/hours

will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century

(depending upon its initial state). If CEB is set to a '0', CB will not toggle. Bits D0 through D2

of register 3 contain the day (day of week). Registers 4, 5 and 6 contain the date (day of

month), month and years. The final register is the control register (this is described in the

clock calibration section). Bit D7 of register 0 contains the STOP bit (ST). Setting this bit to a

'1' will cause the oscillator to stop. If the device is expected to spend a significant amount of

time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0'

the oscillator restarts within one second.

Note: In order to guarantee oscillator start-up after the initial power-up, set the ST bit to a '1,' then

reset this bit to a '0.' This sequence enables a “kick start” circuit which aids the oscillator

start-up during worst case conditions of voltage and temperature.

The seven clock registers may be read one byte at a time, or in a sequential block. The

control register (address location 7) may be accessed independently. Provision has been

made to ensure that a clock update does not occur while any of the seven clock addresses

are being read. If a clock address is being read, an update of the clock registers will be

delayed by 250 ms to allow the read to be completed before the update occurs. This will

prevent a transition of data during the read.

Note: Note: This 250 ms delay affects only the clock register update and does not alter the actual

clock time.

DocID6100 Rev 10 15/25

M41T00 M41T00 clock operation

3.1 Clock calibration

The M41T00 is driven by a quartz controlled oscillator with a nominal frequency of

32768 Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator

frequency error at 25°C, which equates to about ±1.53 minutes per month. With the

calibration bits properly set, the accuracy of each M41T00 improves to better than ±2 ppm at

25 °C.

The oscillation rate of any crystal changes with temperature (see Figure 12). Most clock

chips compensate for crystal frequency and temperature shift error with cumbersome trim

capacitors. The M41T00 design, however, employs periodic counter correction. The

calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by

256 stage, as shown in Figure 13. The number of times pulses are blanked (subtracted,

negative calibration) or split (added, positive calibration) depends upon the value loaded

into the five-bit calibration byte found in the control register. Adding counts speeds the clock

up, subtracting counts slows the clock down.

The calibration byte occupies the five lower order bits (D4-D0) in the control register (addr

7). This byte can be set to represent any value between 0 and 31 in binary form. Bit D5 is a

sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs

within a 64minute cycle. The first 62 minutes in the cycle may, once per minute, have one

second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is

loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a

binary 6 is loaded, the first 12 will be affected, and so on.

Table 5. Register map

(1)

1. Keys:

S = sign bit

FT = frequency test bit

ST = stop bit

OUT = output level

X = don’t care

CEB = century enable bit

CB = century bit

Address

Data

Function/range

BCD format

D7 D6 D5 D4 D3 D2 D1 D0

0 ST 10 seconds Seconds Seconds 00-59

1 X 10 minutes Minutes Minutes 00-59

CEB

(2)

2. When CEB is set to '1', CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century (dependent

upon the initial value set).When CEB is set to '0', CB will not toggle.

CB 10 hours Hours Century/hours 0-1/00-23

3 X X X X X Day Day 01-07

4 X X 10 date Date Date 01-31

5 X X X 10 M. Month Month 01-12

6 10 Years Years Year 00-99

7 OUT FT S Calibration Control

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

M41T00M6F

Mfr. #:

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Manufacturer:

STMicroelectronics

Description:

Real Time Clock Serial 64 (8X8)

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