Si85xx
Preliminary Rev. 0.4 19
3.3.5. Measurement Watchdog Timer and FAULT Output
A built-in watchdog timer disables measurement and holds OUT or OUT1 and OUT2 at their minimum values when
the time between integrator resets exceeds the FAULT
Detect Time. The output signal from this watchdog is
available on the FAULT
output pin (Si8517/8/9 only).
Figure 16 illustrates two means of entering a fault condition. Either fault condition 1 or 2 occurs when the reset
period exceeds the FAULT
Detect Time, which ranges from 30 to 80 µs due process variations. The fault condition
ends when the next logic reset cycle begins.
Figure 16. Measurement Watchdog Timer Operation
t Cycle Reset
FAULT Detect Time
30-80 µs
FAULT Condition 1
FAULT Detect Time
30-80 µs
FAULT Condition 2
Output
Reset Logic
Reset Logic
Output
FAULT Output
FAULT Output
Si85xx
20 Preliminary Rev. 0.4
3.3.6. Output Over-Range
The Si85xx can be over-ranged by more than 100% with no adverse effects. For instance, if the Si8512 (a 10 A
nominal full-scale device) has a 15 A peak current applied, then the output voltage (OUT) will be 3 V (assuming
VDD = 5 V). If a 10 A peak current is applied, then the output returns to the nominal 2 V output. The head room of
OUT is VDD–1.4 V. Figure 17 illustrates the head room limitation of the Si85xx versus supply.
Figure 17. Headroom Limitation
0
1
2
3
4
5
50% 100% 150% 200% 250%
OUT (V)
I (Amps) Percent Nominal Full-Scale Input
VDD = 5 V
VDD = 2.7 V
3.6 V
Si85xx
Preliminary Rev. 0.4 21
3.4. Single-Phase Buck Converter Example
In this example, the Si850x is configured to operate in a single-phase synchronous buck converter (Figure 18).
This converter has a PWM frequency of 1 MHz and a maximum duty cycle of 80%.
This is an example of a half-wave application that can be addressed with Single-Ended output mode. The PWM
period is calculated to be 1/10
–6
= 1.0 µs, and the worst-case value, t
R
, is 0.2 x 1.0 x 10
–6
= 200 ns at 80%
maximum duty cycle (R
TRST
=20k).
In this example, the current measurement is made when the buck switch is on; so, PH2 is chosen as the reset
signal by connecting PH2 to R1 and grounding R2. The PH2 signal can be obtained at the input of the driver
external to the PWM controller or the output of the controller's internal driver (through a resistor divider if the driver
output swings beyond the device VDD range).
Figure 18. Si850x Single-Phase Buck Converter
VDD
VOUT
2 Vpp
IIN
IOUT
L1
C3
Q1
Q2
PH1
PH2
R1
OUT
VDD1
GND1
VIN
Si850x
VDD2
R2
PWM
RESET
PH2
Si850x State
I > 0I = 0
Current
MEASURE
GND2
TRST
R
TRST
100 ns
GND3
C1
0.1 µF
C2
1 µF

SI8501-C-ISR

Mfr. #:
Manufacturer:
Silicon Labs
Description:
SENSOR CURRENT XFMR 5A AC
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