Si85xx
Preliminary Rev. 0.4 25
5. Pin Descriptions—20-Pin SOIC
Figure 22. Example Pin Configurations
Table 13. Si85xx Family Pin Descriptions
Pin# Si850x
Pin Name
Description Si851x
Pin Name
Description
1 VDD1
Power supply input
VDD Power supply input
2 VDD2 MODE Mode control input
3 R1 Integrator reset input 1 R1 Integrator reset input 1
4 R2 Integrator reset input 2 R2 Integrator reset input 2
5 GND2 Ground R3 Integrator reset input 3
6 GND3 R4 Integrator reset input 4
7 OUT Output OUT1 Output in single-ended output mode, or
one of two outputs in Ping-Pong mode.
8 NC No connect OUT2 Second of two Ping-Pong mode outputs
9 TRST Reset time control TRST Reset time control
10 GND1 Ground GND Ground
11–15 IOUT Current output terminal IOUT Current output terminal
16–20 IIN Current input terminal IIN Current input terminal
VDD
MODE
R1
R3
R4
OUT1
R2
OUT2
TRST/FAULT
GND
IIN
IIN
IIN
IIN
IIN
IOUT
IOUT
IOUT
IOUT
IOUT
Si851x
20-Pin SOIC
VDD1
VDD2
R1
GND2
OUT
R2
NC
TRST
GND1
IIN
IIN
IIN
IIN
IIN
IOUT
IOUT
IOUT
IOUT
IOUT
Si850x
20-Pin SOIC
GND3
Si85xx
26 Preliminary Rev. 0.4
6. Ordering Guide
New
OPNs
Full
Scale
Current
(A)
Initial
Accuracy %
1
Temp
Range
Pin 7
Function
Isolation
Rating
Output
Mode
Package
2
Old Obsolete
OPNs
3
(Previously
Specified with
±5% Accuracy
and
–40C to +85 °C)
Old Obsolete
OPNs
3
(Previously
Specified with
±20%
Accuracy)
Si8501-C-IM 5
5%
–40 to
125 °C
Integrator
Reset Pro-
gramming
Time Input
1kV
RMS
Single
QFN-12
Si8501-C-GM Si8504-C-IM
Si8502-C-IM 10 Si8502-C-GM Si8505-C-IM
Si8503-C-IM 20 Si8503-C-GM Si8506-C-IM
Si8501-C-IS 5
5kV
RMS
SOIC-20 New package offeringSi8502-C-IS 10
Si8503-C-IS 20
Si8511-C-IM 5
1kV
RMS
Ping-
Pong
QFN-12
Si8511-C-GM Si8514-C-IM
Si8512-C-IM 10 Si8512-C-GM Si8515-C-IM
Si8513-C-IM 20 Si8513-C-GM Si8516-C-IM
Si8511-C-IS 5
5kV
RMS
SOIC-20 New package offeringSi8512-C-IS 10
Si8513-C-IS 20
Si8517-C-IM 5
FAULT
Output
1kV
RMS
QFN-12
Si8517-C-GM
Si8518-C-IM 10 Si8518-C-GM
Si8519-C-IM 20 Si8519-C-GM
Si8517-C-IS 5
5kV
RMS
SOIC-20 New Package OfferingSi8518-C-IS 10
Si8519-C-IS 20
Notes:
1. See "2.4. Total Measurement Error" on page 11 for more information.
2. All packages are RoHS-compliant. Moisture Sensitivity level is MSL3 with peak reflow temperature of 260 °C according to the JEDEC
industry classification, and peak solder temperature.
3. Since the initial accuracy for all devices is now specified as ±5%, Si8504/5/6 and Si8514/15/16 OPNs have been replaced with
Si8501/2/3 and Si8511/12/13 OPNs, respectively.
Si85xx
Preliminary Rev. 0.4 27
7. Package Outline—12-Pin QFN
Figure 23 illustrates the package details for the Si85xx. Table 14 lists the values for the dimensions shown in the
illustration.
Figure 23. 12-Pin QFN Package Diagram
Table 14. QFN-12 Package Diagram Dimensions
Dimension Min Nom Max
A 0.80 0.85 0.90
A1 0.00 0.03 0.05
b1 0.20 0.25 0.30
b2 0.95 1.00 1.05
D 4.00 BSC.
e 0.50 BSC.
E 4.00 BSC.
f 0.75 BSC.
g 2.45 BSC.
h 1.30 BSC.
L1 0.35 0.40 0.45
L2 0.85 0.90 0.95
aaa 0.05
bbb 0.05
ccc 0.08
ddd 0.10
eee 0.10
Notes:
1. All dimensions shown are in millimeters (mm).
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

SI8501-C-ISR

Mfr. #:
Manufacturer:
Silicon Labs
Description:
SENSOR CURRENT XFMR 5A AC
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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