Low Skew, 1-to-2
LVCMOS / LVTTL Fanout Buffer
8302
Data Sheet
©2016 Integrated Device Technology, Inc Revision D March 4, 20161
GENERAL DESCRIPTION
The 8302 is a low skew, 1-to-2 LVCMOS/LVTTL Fanout
Buffer. The 8302 hasa single ended clock input. The
single endedclock input accepts LVCMOS or LVTTL
input levels. The 8302 features a pair of LVCMOS/
LVTTL outputs. The 8302 is characterized at full 3.3V for
input V
DD
,and mixed 3.3V and 2.5V for output operating
supply modes (V
DDO
). Guaranteed output and part-to-part
skew characteristics make the 8302 ideal for clock distribution
applications demanding well defined performance and
repeatibility.
FEATURES
2 LVCMOS / LVTTL outputs
LVCMOS / LVTTL clock input accepts LVCMOS
or LVTTL input levels
Maximum output frequency: 200MHz
Output skew: 25ps (typical)
Part-to-part skew: 250ps (typical)
Small 8 lead SOIC package saves board space
Full 3.3V or 3.3V core, 2.5V supply modes
0°C to 70°C ambient operating temperature
Lead-Free package fully RoHS compliant
BLOCK DIAGRAM PIN ASSIGNMENT
8302
8-Lead SOIC
3.8mm x 4.8mm, x 1.47mm package body
M Package
Top View
VDDO
VDD
CLK
GND
1
2
3
4
Q0
Q1
CLK
Q0
GND
V
DDO
Q1
8
7
6
5
8302 Data Sheet
©2016 Integrated Device Technology, Inc Revision D March 4, 20162
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
C
PD
Power Dissipation Capacitance
(per output)
V
DD
, V
DDO
= 3.465V 22 pF
V
DD
= 3.465V, V
DDO
= 2.625V 16 pF
R
PULLDOWN
Input Pulldown Resistor 51
kΩ
R
OUT
Output Impedance 5 7 12
Ω
Number Name Type Description
1, 6 V
DDO
Power Output supply pins.
2V
DD
Power Core supply pin.
3 CLK Input Pulldown LVCMOS / LVTTL clock input.
4,7 GND Power Power supply ground.
5 Q1 Output Single clock output. LVCMOS / LVTTL interface levels.
8 Q0 Output Single clock output. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
8302 Data Sheet
©2016 Integrated Device Technology, Inc Revision D March 4, 20163
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, V
DD
= V
DDO
= 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Core Supply Voltage 3.135 3.3 3.465 V
V
DDO
Output Power Supply Voltage 3.135 3.3 3.465 V
I
DD
Power Supply Current 13 mA
I
DDO
Output Supply Current 4mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, V
DD
= V
DDO
= 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage 2 V
DD
+ 0.3 V
V
IL
Input Low Voltage -0.3 0.8 V
I
IH
Input High Current CLK V
DD
= V
IN
= 3.465V 150 µA
I
IL
Input Low Current CLK V
DD
= 3.465V, V
IN
= 0V -5 µA
V
OH
Output High Voltage
50Ω to V
DDO
/2
2.6 V
I
OH
= -100µA 2.9 V
V
OL
Output Low Voltage
50Ω to V
DDO
/2
0.5 V
I
OL
= 100µA 0.2 V
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance, θ
JA
112.7°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifi cations only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Charac-
teristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. AC CHARACTERISTICS, V
DD
= V
DDO
= 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 200 MHz
tp
LH
Propagation Delay, Low-to-High; NOTE 1
ƒ 200MHz
1.9 2.35 2.8 ns
tsk(o) Output Skew; NOTE 2, 4 25 85 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4 250 800 ps
t
R
Output Rise Time 20% to 80% 300 800 ps
t
F
Output Fall Time 20% to 80% 300 800 ps
odc Output Duty Cycle
ƒ 133MHz
45 55 %
133MHz < ƒ 200MHz
40 60 %
Parameters measured at f
MAX
unless otherwise noted.
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 3: Defi ned as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65.

8302AMLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 1:2 LVCMOS Fanout Buffer
Lifecycle:
New from this manufacturer.
Delivery:
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