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ADM1070ART-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
REV. 0
ADM1070
–9–
FUNCTIONAL DESCRIPTION
HOT CIRCUIT INSERTION
Inserting circuit boards into a live –48 V backplane can cause large
transient currents to be drawn as the board capacitance charges up.
These transient currents can cause glitches on the system power
supply and can permanently damage components on the board.
The ADM1070 is designed to control the manner in which a
board’s supply voltage is applied so that harmful transient currents
do not occur and the board can be safely inserted or removed from
a live backplane. Undervoltage, overvoltage, and overcurrent pro-
tection are other features of the part. The ADM1070 ensures that
the input voltage is stable and within tolerance before being applied
to the dc-to-dc converter, which generates the low voltage levels
required to power the on-board logic. One such converter is the
Artesyn EXQ50. Go to www.artesyn.com for more information.
ARTESYN
EXQ50
C
LOAD
ADM1070
LIVE
BACKPLANE
0V
–48V
R
SENSE
PLUG-IN BOARD
R1
R2
V
IN
+
V
IN
–
V
OUT
+
V
OU
T
–
TRIM
FET
Figure 1. Topology
INITIAL STARTUP
The ADM1070 hot swap controller normally resides on a remov-
able circuit board and controls the manner in which power is
applied to the board upon connection. This is achieved using a
FET, Q1, in the power path. By controlling the gate voltage of
the FET, the surge of current to charge load capacitance can be
limited to a safe value when the board makes connection. Note
that the ADM1070 can also reside on the backplane itself, and
perform the same function from there.
TMER
ADM1070
R1
R2
UV/OV
GATE
SENSE
V
EE
Q1
R
SENSE
C
LOAD
V
OUT
R
DROP
16k⍀
V
IN
0V
–48V
LIVE
BACKPLANE
Figure 2. Circuit Board Connection
Figure 2 shows how a plug-in module containing the ADM1070
makes connection to the backplane supply. When the board is
inserted, the –48 V and 0 V lines connect. This powers up the
device with the voltage on V
IN
exceeding V
LKO
.
When the voltage at the UV/OV Pin exceeds undervoltage rising
threshold (V
UVR
) of 0.91 V, it is now inside the operating volt-
age window. It must stay inside this window for the duration of
the power-on reset delay time, t
POR
, which is dependent on the
value of C
T
.
When the device detects that the supply voltage is valid, it ramps
up the gate voltage until the FET turns on and the load current
increases. The ADM1070 monitors the level of the current flowing
through the FET by sensing the voltage across the external
sense resistor, R
SENSE
. When the sense voltage reaches 100 mV,
the GATE Pin is actively controlled, limiting the load current.
In this way, the maximum current permitted to flow through the
load is set by the choice of R
SENSE
.
If a change in the level of the supply voltage causes UV/OV to
fall below the undervoltage falling threshold of V
UVF
, or rise
above the overvoltage rising threshold of V
OVR
, then the gate
drive will be disabled.
BOARD REMOVAL
If the board is removed from a card cage, the voltage at the
UV/OV pin falls to zero (i.e., outside operating range) and the
gate drive is deasserted, turning off the FET.
CONTROLLING THE CURRENT
The ADM1070 features a current limiting function that protects
against short circuits or excessive supply currents. The flow of
current through the load is monitored by measuring the voltage
across the sense resistor, which is connected between the SENSE
and V
EE
Pins. There are three different types of protection offered:
1. If the voltage across the sense resistor exceeds the circuit
breaker limit voltage of 88 mV (rising) for the current limit
on time (t
LIMITON
), then a current fault has occurred and the
PWM cycle begins. The FET current is linearly controlled at
a maximum of 100 mV/R
SENSE
(via the gate drive) during
t
LIMITON
(see next section). The gate is then disabled for the
duration t
OFF
. This PWM ratio, which will always be 3%, is
given by t
ON
/t
OFF
.
A unique feature of the ADM1070 is the limited consecutive
retry function. An internal fault counter keeps track of the
number of successive PWM cycles that occur. The fault
counter is incremented after every fault is detected. If the
ADM1070 detects seven consecutive current faults, it is appar-
ent that the fault is not a temporary one and the device
latches itself off. The fault counter is cleared if a new t
ON
timeout does not occur within 2 ⫻ t
OFF
of the previous
t
LIMITON
timeout.
REV. 0–10–
ADM1070
2. If a voltage between the SENSE and V
EE
Pins increases to
100 mV (the analog current limit voltage) during t
LIMITON
,
then the ADM1070 takes action to reduce this current to a
safer level. The internal analog current limit loop dynami-
cally adjusts the gate drive, keeping the load current at the
100 mV/R
SENSE
level. The FET now acts as a current
source, limiting the load current to the level set by the value
of the sense resistor.
The sense voltage is also above the circuit breaker limit voltage,
so the limited consecutive retry function is still operational. If
the current fault is not cleared (sense resistor voltage brought
below 79 mV) after seven consecutive faults, then the device
is latched off.
3. If a serious short circuit occurs on the load side, the –48 V
supply can cause massive currents to flow very quickly.
Because of this, the gate voltage must be reduced quickly to
prevent a catastrophic failure. If the ADM1070 detects a
voltage greater than the fast current limit voltage (126 mV)
across the sense resistor, it is apparent that a serious short
circuit is present and the load current must be reduced as
quickly as possible. The fast current limit loop takes over and
pulls gate low much faster than in the previous case.
SENSE RESISTOR
The ADM1070’s current limiting function can operate at differ-
ent current levels. The sense resistor is inserted between the V
EE
and sense pins, and a current fault occurs whenever the voltage
across the sense resistor is greater than 100 mV for longer than
the on time, t
LIMITON
. The current limit is determined by selec-
tion of the sense resistor, R
SENSE
. Table I shows how the
maximum allowable load current (I
LOAD(MAX)
) and the mini-
mum and maximum in-rush currents (I
LIMIT(MIN)
) and I
LIMIT(MAX)
)
are related to the value of R
SENSE
.
R
SENSE
I
LOAD(MAX)
I
LIMIT(MIN)
I
LIMIT(MAX)
(m⍀) (A) (A) (A)
5 12.0 18.0 22.0
10 6.0 9.0 11.0
15 4.0 6.0 7.3
18 3.3 5.0 6.1
22 2.7 4.1 5.0
33 1.8 2.7 3.3
47 1.3 1.9 2.3
51 1.2 1.7 2.2
68 0.9 1.3 1.6
75 0.8 1.2 1.5
90 0.7 1.0 1.2
SHUNT REGULATOR
A shunt regulator shunts the ADM1070 V
IN
Pin. Power is
derived from the –48 V supply through the combination of an
internal Zener diode and an external shunt resistor, R
DROP
.
Table II shows the operational voltage range and power dissipa-
tion for different values of R
DROP
. Note that 16 kΩ is the default
value for R
DROP
.
Min Allowable Max Allowable P
DROP
V
DD
Voltage V
DD
Voltage @ 48 V
R
DROP
(V) (V) (W)
10 kΩ (0.25 W)
26 61 0.13
12 kΩ 28.6 65.8 0.11
14 kΩ 31.2 70.2 0.09
16 kΩ 33.8 74.2 0.08
18 kΩ 36.4 78.1 0.07
20 kΩ 39 81.7 0.065
22 kΩ 41.6 85.2 0.06
10 kΩ (0.5 W) 26 81.7 0.13
12 kΩ 28.6 88.5 0.11
14 kΩ 31.2 94.7 0.09
16 kΩ 33.8 100.4 0.08
18 kΩ 36.4 105.9 0.07
20 kΩ 39 111 0.065
22 kΩ 41.6 115.9 0.06
INTERNAL UNDERVOLTAGE LOCKOUT
The V
IN
Pin is monitored for undervoltage lockout. When the
voltage at V
IN
is above 8.5 V (V
LKO
), the device is enabled. If
this voltage drops below 8.5 V, the device is disabled and gate is
pulled low. Note that this is unrelated to the undervoltage
and overvoltage functions performed at the UV/OV Pin.
TIMER
The TIMER Pin on the ADM1070 gives the user control over
the timing functions on the part. By connecting an external
capacitor between the TIMER Pin and V
EE
, the user can set the
UV/OV glitch filter time, t
FLT
, the power-on reset delay time,
t
POR
, the maximum current on time, t
ON
, the current limit time
out, t
OFF
, and the continuous short circuit time before latched
shutdown, t
SHORT
(see Table III). Note that all times are scaled
relative to each other and cannot be altered individually (without
changing the other times). The default values for these times are
selected by tying the TIMER Pin directly to V
EE
.
Table III. Timer Capacitor Values and Timing Values
C
TIMER
t
FLT
t
POR
t
LIMITON
t
PWMOFF
t
SHORT
(pF) (ms) (ms) (ms) (ms) (ms)
220 0.58 0.58 4.8 150 1000
330 0.85 0.85 7.1 230 1400
470 1.21 1.21 9.9 320 2000
Tied to V
EE
1.55 1.55 12.8 410 2600
680 1.74 1.74 14.2 450 2800
1000 2.54 2.54 20.8 660 4100
2200 5.64 5.64 46.2 1465 9113
Table I. I
LOAD(MAX)
, I
LIMIT(MIN)
, and I
LIMIT(MAX)
for Different Values of R
SENSE
Table II. Minimum and Maximum Allowable Operating
Voltages for Different Values of R
DROP
REV. 0
ADM1070
–11–
UNDERVOLTAGE/OVERVOLTAGE DETECTION
The ADM1070 incorporates single-pin overvoltage and
undervoltage detection with a programmable operating voltage
window. When
the voltage on the
UV/OV pin rises above the
OV rising threshold or falls below the UV falling threshold, a
fault signal is generated that disables the linear current regulator
and results in the GATE Pin being pulled low. The voltage fault
signal is time filtered so that faults of duration less than the UV/
OV glitch filter time, t
FLT
, do not force the gate drive low (t
FLT
is set by the choice of external capacitor C
T
, see Table III). The
filter operates only on
the “faulting” edge (i.e., on a high to
low transition on the
undervoltage monitor and on a low to
high transition on the overvoltage monitor). The analog com-
parators have some hysteresis to provide smooth switching of
the comparator inputs.
If the voltage on UV/OV goes out of range (i.e., below 0.86 V
or
above 1.97 V) gate is pulled low. If
the UV/OV voltage
subse
quently re-enters the operating voltage window, the
ADM1070
will
restore the gate drive.
The overvoltage and undervoltage thresholds are:
UV turning on = 0.91 V
UV turning off = 0.86 V
OV turning on = 1.97 V
OV turning off = 1.93 V
The undervoltage/overvoltage levels are determined by selection
of the resistor ratio R1/R2, (see Table I). These two resistors
form a resistor divider that generates the voltage; at the UV/OV
Pin, which
is proportional to the supply voltage. By choosing
this ratio
carefully, the ADM1070 can be programmed to apply
the supply voltage to the load only when it is within specific
thresholds.
For example, for R1 = 39 kΩ and R2 = 1 kΩ the
typical operating range is 36.4 V to 76.8 V. The undervoltage
and
overvoltage
shutdown thresholds are 34.4 V and 77.2 V
for this resistor
ratio. 1% resistors should be used to maintain
the accuracy of these threshold levels.
Voltage Divider:
V
UV/OV
= V
SS
(R2/(R1 + R2))
For R2 = 1 kΩ:
V
SS
= V
UV/OV
(R1 + 1)
And for R1 = 39 kΩ:
V
SS
= 40 V
UV/OV
Operating Range:
UV => 40(0.91) = 36.4 V
OV => 40(1.93) = 77.2 V
UV/OV Shutdown Levels:
UV => 40(0.86) = 34.4 V
OV => 40(1.97) = 78.8 V
V
SS
––
+
+
R1
R2
V
UV/OV
Figure 3. Voltage Divider
R1 – k⍀ (FOR R2 = 1k⍀)
0
OPERATING VOLTAGE – V
36
40
20
80
60
100
120
30 47 5133 4339
Figure 4. Operating Voltage Window vs. Resistance Ratio
V
61.0
67.0
72.9
78.8
86.7
94.6
102.4
Resistor Ratio Undervoltage Overvoltage
R1 (for R2 = 1 k⍀)V
UV
(Falling) V
UV
(Rising) V
OV
(Falling) V
OV
(Rising)
k⍀
30
33
36
39
43
47
51
Ta ble IV. Resistance Ratios and Operating Voltage Windows
V
26.7
29.2
31.8
34.4
37.8
41.3
44.7
V
28.2
31.0
33.7
36.4
40.0
43.7
46.4
V
59.8
65.6
71.4
77.2
84.9
92.6
100.4
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

ADM1070ART-REEL7

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Description:
Hot Swap Voltage Controllers 6-Pin -48V Hot Swap Controller I.C.
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