REV. 0–12–
ADM1070
FUNCTIONALITY AND TIMING
Live Insertion
The timing waveforms associated with the live insertion of a
plug-in board using the ADM1070 are shown in the following
figures. When the board connects the GND-V
EE
potential
climbs to 48 V. As this voltage is applied, the voltage at the V
IN
Pin ramps above the undervoltage lockout (V
LKO
) of 8.5 V to a
constant 12.3 V and is held at this level with the shunt resistor
and external resistor combination at the V
IN
Pin.
When UV/OV crosses the undervoltage rising threshold of
0.91 V, it is now inside the operating voltage window and the
–48 V supply must be applied to the load. After a time delay,
t
POR
, the ADM1070 begins to ramp up the gate drive. When the
voltage on the SENSE Pin reaches 100 mV (the analog current
limit) the gate drive is held constant. When the board capaci-
tance is fully charged, the sense voltage begins to drop below
the analog current limit voltage and the gate voltage is free to
ramp up further. The gate voltage eventually reaches its maxi-
mum value of 12.3 V (as set by V
IN
).
GND-V
EE
t
POR
V
IN
UV/OV
GATE
SENSE
V
OUT
V
LKO
V
UVR
Figure 5. Timing Waveforms Associated with a
Live Insertion Event
GATE
SENSE
V
OUT
CH25.00VCH1
10.00VCH3
100mV M 500s CH1 2.8V
T
T
Figure 6. Start-Up Sequence
OVERVOLTAGE AND UNDERVOLTAGE
The waveforms for an overvoltage glitch are shown below.
When UV/OV glitches above the overvoltage rising threshold of
1.97 V, an overvoltage condition is detected and the gate volt-
age is pulled low. UV/OV begins to drop a back toward the
operating voltage window and the gate drive is restored when
the overvoltage falling threshold of 1.93 V is reached. Figure 7
illustrates the ADM1070’s operation in an overvoltage situation.
GATE
SENSE
V
UV/OV
CH210.00VCH1
1.00VCH3
100mV M 200s CH3 1.96V
T
T
Figure 7. Timing Waveforms Associated with an
Overvoltage Glitch
An undervoltage glitch is dealt with in a similar way. When
V
UV/OV
falls below the undervoltage falling threshold of 0.86 V,
the gate voltage is pulled low. If UO/UV subsequently rises
back above the undervoltage rising threshold of 0.91 V, then the
gate voltage is restored. Figure 8 illustrates the ADM1070’s
operation in an undervoltage situation.
GATE
SENSE
V
UV/OV
CH210.0VCH1
1.00VCH3
100mV M 200ms
Figure 8. Timing Waveforms Associated with an
Undervoltage Glitch
REV. 0
ADM1070
–13–
CURRENT FAULT PLOTS
Some timing waveforms associated with current over faults are
shown in the following figures. Figure 9 shows how a current
glitch (of approximately 500 µs) is dealt with when the output is
shorted after power-up. The gate voltage is at a constant 12.3 V
before the glitch occurs. When the short circuit occurs, the
sense voltage rises sharply as the load current ramps up quickly.
When the sense voltage reaches 100 mV (V
ACL
), the ADM1070
reduces the gate voltage to stop the load current from increasing
any further. When V
SENSE
drops back below V
ACL
, the gate
voltage is increased again.
GATE
SENSE
V
OUT
CH3
10.00VCH1
20.00V
CH2
100mV M 500s CH2
34mV
T
T
T
Figure 9. Timing Waveforms Associated with a
Current Glitch
The plots shown illustrate the operation of the ADM1070’s
unique limited consecutive retry function. Figure 10 highlights
what happens when a current fault occurs for more than 14 ms
(default t
LIMITON
when TIMER Pin tied to V
EE
) and a current
fault is registered. In this case, gate is previously low and
the
part is being powered up into a current fault situation
(shorted
load). When power is applied, gate is allowed to ramp until
sense reaches 100 mV. gate is then held constant to keep sense
at this level. After t
ON
, the PWM cycle begins and gate is
reduced to zero.
5.00V CH2 100mV
M 5.00s
CH1 1.4VCH1
GATE
SENSE
14ms
Figure 10. Timing Waveforms Associated with a
Current Fault
Figure 11 shows a current fault on a wider timebase. The first
spike on the sense line represents the first current fault. The
sense voltage is allowed to ramp up to 100 mV before the gate
voltage is reduced to compensate. The gate and sense voltages
remain at these levels until the t
ON
time has expired. A current
fault is then registered and the gate voltage, and therefore the
sense voltage, are then both held low for the time period t
OFF
.
Note that the PWM ratio (t
ON
/t
OFF
) is equal to 3%. The cycle
then restarts and the sense voltage is free to ramp up to 100 mV
again (it will if the fault is still present). This cycle repeats itself
a total of seven times. Figure 12 shows the seven consecutive
faults occurring on an even wider timebase. If the ADM1070
detects seven consecutive current faults, the part then latches off
(after a total time t
SHORT
).
GATE
SENSE
5.00V
CH2
1.00VCH3
100mV M 100ms
CH1
t
ON
t
OFF
Figure 11. Illustration of the PWM Ratio (t
ON
/t
OFF
)
GATE
SENSE
5.00V
CH2
1.00VCH3
100mV M 100ms
CH1
t
SHORT
Figure 12. Illustration of the Limited Consecutive
Retry Function (Seven Retries and Latch Off)
REV. 0–14–
ADM1070
Figure 13 shows the behavior of ADM1070 when a temporary
current fault occurs followed by a permanent current fault.
When the first overcurrent fault occurs, the first 100 mV spike
on the sense line can be seen. During the t
OFF
time, this current
fault corrects itself. After this time period, a no fault condition is
detected and the limited consecutive counter is reset. GATE is
reasserted. When the overcurrent fault returns permanently, the
limited consecutive retry counter detects seven consecutive
faults and the part latches off.
GATE
SENSE
5.00VCH2100mV M 500ms
CH1
B
N
T
Figure 13. Illustration of the PWM Ratio (t
ON
/t
OFF
)
In this way, the ADM1070 prevents nuisance shutdowns from
transient shorts of up to three seconds (typically), but will provide
latched shut-down protection from permanently shorted loads.
KELVIN SENSE RESISTOR CONNECTION
When using a low value sense resistor for high current measure-
ment, the problem of parasitic series resistance can arise. The
lead resistance can be a substantial fraction of the rated resis-
tance, making the total resistance a function of lead length. This
problem can be avoided by using a Kelvin sense connec
tion.
This type of connection separates the current path
through
the resistor and the voltage drop across the resistor. Figure 14
shows the correct way to connect the sense resistor between the
SENSE and V
EE
Pins of the ADM1070.
KELVIN SENSE TRACES
CURRENT
FLOW FROM
LOAD
CURRENT
FLOW TO –48V
BACKPLANE
SENSE RESISTOR
SENSE V
EE
ADM1070
Figure 14. Kelvin Sensing with the ADM1070
UV/OV AS ENABLE PIN
Connecting an open collector output to the UV/OV Pin means
that a TTL signal can be used to disable the part. In Figure 15,
the open collector output connects to EN. Driving the base of
the open collector device high enough to cause the UV/OV Pin
to be pulled below the undervoltage falling threshold of 0.86 V
typical will cause the pass transistor Q1 to be turned off.
EN
ADM1070
0V
–48V
R1
R2
R
DROP
V
IN
UV/OV
TIMER
GATE
SENSE
V
EE
C
LOAD
V
OUT
Q1
R
SENSE
Figure 15. UV/OV Used as Enable Input

ADM1070ART-REEL7

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Hot Swap Voltage Controllers 6-Pin -48V Hot Swap Controller I.C.
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