2©2016 Integrated Device Technology, Inc Revision A January 27, 2016
874328I-01 Data Sheet
Table 1. Pin Descriptions
Number Name Type Description
1, 17, 32, 49, 64 V
EE
Power
Negative supply pins.
2V
CCOA
Power
Output power supply for Bank A outputs.
3, 4 QA0, nQA0 Output
Differential Bank A output pair. LVPECL interface levels.
5, 6 QA1, nQA1 Output
Differential Bank A output pair. LVPECL interface levels.
7, 8 QA2, nQA2 Output
Differential Bank A output pair. LVPECL interface levels.
9, 10 QB0, nQB0 Output
Differential Bank B output pair. LVPECL interface levels.
11, 12 QB1, nQB1 Output
Differential Bank B output pair. LVPECL interface levels.
13, 14 QB2, nQB2 Output
Differential Bank B output pair. LVPECL interface levels.
15 V
CCOB
Power
Output power supply for Bank B outputs.
16 CLK_EN Input Pullup Clock enable. See Table 3G for function. LVCMOS/LVTTL interface levels.
18, 31 V
CCODE
Power
Output power supply for Bank D and E outputs.
19, 20 QE0, nQE0 Output
Differential Bank E output pair. LVDS interface levels.
21, 22 QE1, nQE1 Output
Differential Bank E output pair. LVDS interface levels
23, 24 QE2, nQE2 Output
Differential Bank E output pair. LVDS interface levels
25, 26 QD0, nQD0 Output
Differential Bank D output pair. LVDS interface levels.
27, 28 QD1, nQD1 Output
Differential Bank D output pair. LVDS interface levels.
29, 30 QD2, nQD2 Output
Differential Bank D output pair. LVDS interface levels.
33 OEA Input Pullup
Output enable for Bank A outputs. See Table 3A for function.
LVCMOS/LVTTL interface levels.
34 OEB Input Pullup
Output enable for Bank B outputs. See Table 3B for function.
LVCMOS/LVTTL interface levels.
35 CLK Input
Non-inverting differential LVPECL clock input.
36 V
T
Termination
input
Input for termination. Both CLK and nCLK inputs are terminated to this pin.
See input termination information in the applications section.
37 V
REF
Output
Reference voltage output. Provides a bias voltage of V
CC
- 1.10V. Connect
the V
REF
output to V
T
if the differential input pair CLK, nCLK is AC-coupled.
Leave V
REF
open if the differential input pair CLK, nCLK is DC-coupled. See
input termination information in the applications section.
38 nCLK Input
Inverting differential LVPECL clock input.
39 OEC Input Pullup
Output enable for Bank C outputs. See Table 3C for function.
LVCMOS/LVTTL interface levels.
40 V
CC
Power
Power supply pin.
41 OED Input Pullup
Output enable for Bank D outputs. See Table 3D for function.
LVCMOS/LVTTL interface levels.
42 OEE Input Pullup
Output enable for Bank E outputs. See Table 3E for function.
LVCMOS/LVTTL interface levels.
43, 44 QC0, nQC0 Output
Differential Bank C output pairs. LVPECL interface levels.
Continued on next page.
