7©2016 Integrated Device Technology, Inc Revision A January 27, 2016
874328I-01 Data Sheet
Table 5. AC Electrical Characteristics, V
CC
= V
CCOA
= V
CCOB
= V
CCOC
= = V
CCODE
= V
CCOF
= 2.5V ± 5%, V
EE
= 0V,
T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the differential cross points.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
REF
Input Frequency 614.4 650 MHz
f
OUT
Output
Frequency
QA[0:2] 614.4 650 MHz
Q[Bx:Fx] 153.6 162.5 MHz
t
JIT
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
f
REF
= 614.4MHz,
Integration Range: 10Hz – 10MHz
0.05 ps
t
PD
Propagation Delay; NOTE 1
CLK to any QA, QB or QC output 1.2 4.2 ns
CLK to any QD, QE or QF output 2.0 4.8 ns
tsk(b) Bank Skew; NOTE 2, 3 Within each output Bank 65 ps
tsk(o) Output Skew; NOTE 3, 4
Across output Banks QA, QB and QC 50 ps
Across output Banks QD, QE and QF 65 ps
Across all output Banks QA to QF 70 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5 Within each output bank 250 ps
odc
Output
Duty Cycle
QA[0:2] 45 55 %
Q[Bx:Fx] 48 52 %
t
R
/ t
F
Output
Rise/ Fall Time
QA[0:2] 20% to 80% 200 400 ps
Q[Bx:Fx] 20% to 80% 300 600 ps
8©2016 Integrated Device Technology, Inc Revision A January 27, 2016
874328I-01 Data Sheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a Phase
noise plot and is most often the specified plot in many applications.
Phase noise is defined as the ratio of the noise power present in a
1Hz band at a specified offset from the fundamental frequency to the
power value of the fundamental. This ratio is expressed in decibels
(dBm) or a ratio of the power in the 1Hz band to the power in the
fundamental. When the required offset is specified, the phase noise
is called a dBc value, which simply means dBm at a specified offset
from the fundamental. By investigating jitter in the frequency
domain, we get a better understanding of its effects on the desired
application over the entire time record of the signal. It is
mathematically possible to calculate an expected bit error rate given
a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device.
This is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator “IFR2042 10kHz – 56.4GHz Low Noise Signal
Generator as external input to an Agilent 8133A 3GHz Pulse
Generator.
9©2016 Integrated Device Technology, Inc Revision A January 27, 2016
874328I-01 Data Sheet
Parameter Measurement Information
LVPECL Output Load AC Test Circuit
Differential Input Level
Output Skew
LVDS Output Load AC Test Circuit
Part-to-Part Skew
Bank Skew
SCOPE
Qx
nQx
V
EE
2V
-0.5V ± 0.125V
V
CC,
V
CCOA,
V
CCOB,
V
CCOC
nCLK
CLK
V
CC
V
EE
V
IH
Cross Points
V
IN
V
IL
nQx
Qx
nQy
Qy
V
CC,
V
CCODE,
V
CCOF
tsk(pp)
V
DDOX
2
V
DDOX
2
Part 1
Part 2
Qx
Qy
nQXx
QXx
nQXx
QXx
tsk(b)
Where X = Bank A, B, C, D, E or F

874328BYI-01LF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 2.5V Differential Clock Divider/Buffer
Lifecycle:
New from this manufacturer.
Delivery:
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