AD7243BRZ-REEL Datasheet AD7243ARZ-REEL, AD7243ARZ, AD7243ANZ | P10-P12

REV. A

–9–

AD7243

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD7243 is via a serial bus

which uses standard protocol compatible with DSP processors

and microcontrollers. The communications channel requires a

three-wire interface consisting of a clock signal, a data signal

and a synchronization signal. The AD7243 requires a 16-bit

data word with data valid on the falling edge of SCLK. For all

the interfaces, the DAC update may be done automatically

when all the data is clocked in or it may be done under control

of LDAC.

Figures 11 to 16 show the AD7243 configured for interfacing to

a number of popular DSP processors and microcontrollers.

AD7243–ADSP-2101/ADSP-2102 Interface

Figure 11 shows a serial interface between the AD7243 and the

ADSP-2101/ADSP-2102 DSP processor. The ADSP-2101/

ADSP-2102 contains two serial ports, and either port may be

used in the interface. The data transfer is initiated by TFS going

low. Data from the ADSP-2101/ADSP-2102 is clocked into the

AD7243 on the falling edge of SCLK. When the data transfer is

complete, TFS is taken high. In the interface shown the DAC is

updated using an external timer which generates an LDAC

pulse. This could also be done using a control or decoded ad-

dress line from the processor. Alternatively, the LDAC input

could be hard wired low and in this case the update takes place

automatically on the sixteenth falling edge of SCLK.

ADSP - 2101/

ADSP - 2102*

TIMER

TFS

SCLK

LDAC

SYNC

SCLK

SDIN

AD7243*

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 11. AD7243–ADSP-2101/ADSP-2102 Interface

AD7243–DSP56000 Interface

A serial interface between the AD7243 and the DSP56000 is

shown in Figure 12. The DSP56000 is configured for Normal

Mode Asynchronous operation with Gated Clock. It is also set

up for a 16-bit word with SCK and SC2 as outputs and the FSL

control bit set to a “0.” SCK is internally generated on the

DSP56000 and applied to the AD7243 SCLK input. Data from

the DSP56000 is valid on the falling edge of SCK. The SC2

output provides the framing pulse for valid data. This line must

be inverted before being applied to the SYNC input of the

AD7243.

The LDAC input of the AD7243 is connected to DGND so the

update of the DAC latch takes place automatically on the six-

teenth falling edge of SCLK. An external timer could also be

used as in the previous interface if an external update is

required.

DSP56000

SCK

STD

SC2

LDAC

SCLK

SDIN

AD7243*

SYNC

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 12. AD7243–DSP56000 Interface

AD7243–TMS32020 Interface

Figure 13 shows a serial interface between the AD7243 and the

TMS32020 DSP processor. In this interface, the CLKX and

FSX signals for the TMS32020 should be generated using ex-

ternal clock/timer circuitry. The FSX pin of the TMS32020

must be configured as an input. Data from the TMS32020 is

valid on the falling edge of CLKX.

The clock/timer circuitry generates the LDAC signal for the

AD7243 to synchronize the update of the output with the serial

transmission. Alternatively, the automatic update mode may be

selected by connecting LDAC to DGND.

LDAC

SYNC

SCLK

SDIN

AD7243*

*ADDITIONAL PINS OMITTED FOR CLARITY

CLOCK/

TIMER

TMS32020

FSX

CLKX

Figure 13. AD7243–TMS32020 Interface

AD7243

–10–

REV. A

AD7243–87C51 Interface

A serial interface between the AD7243 and the 87C51

microcontroller is shown in Figure 14. TXD of the 87C51 drives

SCLK of the AD7243, while RXD drives the serial data line of

the part. The SYNC signal is derived from the port line P3.3.

The 87C51 provides the LSB of its SBUF register as the first bit

in the serial data stream. Therefore, the user will have to ensure

that the data in the SBUF register is arranged correctly so that

the don’t care bits are the first to be transmitted to the AD7243

and the last bit to be sent is the LSB of the word to be loaded to

the AD7243. When data is to be transmitted to the part, P3.3 is

taken low. Data on RXD is valid on the falling edge of TXD.

The 87C51 transmits its serial data in 8-bit bytes with only eight

falling clock edges occurring in the transmit cycle. To load data

to the AD7243, P3.3 is left low after the first eight bits are trans-

ferred and a second byte of data is then transferred serially to the

AD7243. When the second serial transfer is complete, the P3.3

line is taken high.

Figure 14 shows the LDAC input of the AD7243 hard wired

low. As a result, the DAC latch and the analog output will be up-

dated on the sixteenth falling edge of TXD after the SYNC sig-

nal for the DAC has gone low. Alternatively, the scheme used in

previous interfaces, whereby the LDAC input is driven from a

timer, can be used.

LDAC

SCLK

SDIN

AD7243*

SYNC

*ADDITIONAL PINS OMITTED FOR CLARITY

P3.3

TXD

RXD

87C51*

Figure 14. AD7243–87C51 Interface

AD7243–68HC11 Interface

Figure 15 shows a serial interface between the AD7243 and the

68HC11 microcontroller. SCK of the 68HC11 drives SCLK of

the AD7243 while the MOSI output drives the serial data line of

the AD7243. The SYNC signal is derived from a port line (PC7

shown).

For correct operation of this interface, the 68HC11 should be

configured such that its CPOL bit is a 0 and its CPHA bit is a 1.

When data is to be transmitted to the part, PC7 is taken low.

When the 68HC11 is configured like this, data on MOSI is valid

on the falling edge of SCK. The 68HC11 transmits its serial data

in 8-bit bytes with only eight falling clock edges occurring in the

transmit cycle. To load data to the AD7243, PC7 is left low after

the first eight bits are transferred and a second byte of data is

then transferred serially to the AD7243. When the second serial

transfer is complete, the PC7 line is taken high.

Figure 15 shows the LDAC input of the AD7243 hardwired

low. As a result, the DAC latch and the analog output of the

DAC will be updated on the sixteenth falling edge of SCK after

the respective SYNC signal has gone low. Alternatively, the

scheme used in previous interfaces, whereby the LDAC input is

driven from a timer, can be used.

LDAC

SCLK

SDIN

AD7243*

SYNC

*ADDITIONAL PINS OMITTED FOR CLARITY

PC7

SCK

MOSI

68HC11*

Figure 15. AD7243–68HC11 Interface

Multiple DAC Daisy-Chain Interface

A multi-DAC serial interface is shown in Figure 16. This

scheme may be used with all of the interfaces previously dis-

cussed if more than one DAC is required in a system. To enable

the facility the DCEN pin must be connected high on all de-

vices, including the last device in the chain.

SCLK

AD7243*

SYNC

LDAC

*ADDITIONAL PINS OMITTED FOR CLARITY

PA1

PA2

PA3

MICROCONTROLLER

PA0

SDIN

DCEN

SDO

SCLK

AD7243*

SYNC

LDAC

SDIN

DCEN

SDO

SCLK

AD7243*

SYNC

LDAC

SDIN

DCEN

SDO

Figure 16. AD7243 Daisy-Chain Configuration

REV. A

–11–

AD7243

Common clock, data, and synchronization signals are applied to

all DACs in the chain. The loading sequence starts by taking

SYNC low. The data is then clocked into the input registers on

the falling edge of SCLK. Sixteen clock pulses are required for

each DAC in the chain. The data ripples through the input reg-

isters with the first 16-bit word filling the last register in the

chain after 16N clock pulses where N = the total number of

DACs in the chain.

When valid data has been loaded into all the registers, the

SYNC input should be taken high and a common LDAC pulse

used to update all the DACs simultaneously.

APPLICATIONS

OPTO-ISOLATED INTERFACE

In many process control type applications it is necessary to pro-

vide an isolation barrier between the controller and the unit be-

ing controlled. Opto-isolators can provide voltage isolation in

excess of 3 kV. The serial loading structure of the AD7243

makes it ideal for opto-isolated interfaces as the number of in-

terface lines is kept to a minimum.

Figure 17 shows a 4-channel isolated interface using the

AD7243. The DCEN pin must be connected high to enable the

daisy-chain facility. Four channels with 12-bit resolution are

provided in the circuit shown, but this may be expanded to ac-

commodate any number of DAC channels without any extra

isolation circuitry.

The sequence of events to program the output channels is as

follows:

1. Take the SYNC line low.

2. Transmit the data as four 16-bit words. A total of 64 clock

pulses is required to clock the data through the chain.

3. Take the SYNC line high.

4. Pulse the LDAC line low. This updates all output channels

simultaneously on the falling edge of LDAC.

To reduce the number of opto-couplers, the LDAC line could

be driven from a one shot which is triggered by the rising edge

on the SYNC line. A low level pulse of 50 ns duration or greater

is all that is required to update the outputs.

SCLK

AD7243*

SYNC

LDAC

SDIN

DCEN

SDO

SCLK

AD7243*

SYNC

LDAC

SDIN

DCEN

SDO

SCLK

AD7243*

SYNC

LDAC

SDIN

DCEN

SDO

SCLK

AD7243*

SYNC

LDAC

SDIN

DCEN

SDO

OUT

*ADDITIONAL PINS OMITTED FOR CLARITY

DATA OUT

CLOCK OUT

SYNC OUT

CONTROL OUT

CONTROLLER

OUT

)

QUAD OPTO-COUPLER

OUT

)

OUT

)

OUT

)

OUT

Figure 17. Four-Channel Opto-lsolated Interface

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

AD7243BRZ-REEL

Mfr. #:

Buy AD7243BRZ-REEL

Manufacturer:

Analog Devices Inc.

Description:

Digital to Analog Converters - DAC CMOS 12B SERIAL IC

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

AD7243BRZ-REEL

AD7243BRZ-REEL

Products related to this Datasheet