AD7243BRZ-REEL Datasheet AD7243ARZ-REEL, AD7243ARZ, AD7243ANZ | P7-P9

AD7243

–6–

REV. A

0 V, to allow full sink capability of 2.5 mA over the entire

output range and to eliminate the effects of negative offsets on

the transfer characteristic (outlined previously). A plot of the

output sink capability of the amplifier is shown in Figure 5.

6810

OUTPUT VOLTAGE – Volts

V = –15V

V = 0V

I – mA

SINK

Figure 5. Amplifier Sink Current

DIGITAL INTERFACE

The AD7243 contains an input serial to parallel shift register

and a DAC latch. A simplified diagram of the input loading

DAC LATCH (12 BITS)

INPUT SHIFT REGISTER (16 BITS)

GATING

SIGNAL

GATED

SCLK

SDO

RESET

COUNTER/

DECODER

AUTO – UPDATE

CIRCUITRY

DCEN

SYNC

SCLK

SDIN

LDAC

CLR

Figure 6. Simplified Loading Structure

SCLK

DB11

MSB

DB14

DB13

DB12

DB0

LSB

= DON'T CARE

SDIN

SYNC

LDAC

CLR

DB15

Figure 7. Timing Diagram (Standalone Mode)

circuitry is shown in Figure 6. Serial data on the SDIN input is

loaded to the input register under control of DCEN, SYNC and

SCLK. When a complete word is held in the shift register, it

may then be loaded into the DAC latch under control of

LDAC. Only the data in the DAC latch determines the analog

output on the AD7243.

The DCEN (daisy-chain enable) input is used to select either a

standalone mode or a daisy-chain mode. The loading format is

slightly different depending on which mode is selected.

Serial Data Loading Format (Standalone Mode)

With DCEN at Logic 0 the standalone mode is selected. In this

mode a low SYNC input provides the frame synchronization

signal which tells the AD7243 that valid serial data on the SDIN

input will be available for the next 16 falling edges of SCLK. An

internal counter/decoder circuit provides a low gating signal so

that only 16 data bits are clocked into the input shift register.

After 16 SCLK pulses the internal gating signal goes inactive

(high) thus locking out any further clock pulses. Therefore, ei-

ther a continuous clock or a burst clock source may be used to

clock in the data.

The SYNC input should be taken high after the complete 16-bit

word is loaded in.

REV. A

–7–

AD7243

Although 16 bits of data are clocked into the input register, only

the latter 12 bits get transferred into the DAC latch. The first 4

bits in the 16 bit stream are don’t cares since their value does

not affect the DAC latch data. Therefore, the data format is 4

don’t cares followed by the 12-bit data word with the LSB as

the last bit in the serial stream.

There are two ways in which the DAC latch and hence the ana-

log output may be updated. The status of the LDAC input is

examined after SYNC is taken low. Depending on its status, one

of two update modes is selected.

If LDAC = 0, then the automatic update mode is selected. In

this mode the DAC latch and analog output are updated auto-

matically when the last bit in the serial data stream is clocked in.

The update thus takes place on the sixteenth falling SCLK edge.

If LDAC = 1, then the automatic update is disabled and the

DAC latch is updated by taking LDAC low any time after the

16-bit data transfer is complete. The update now occurs on the

falling edge of LDAC. Note that the LDAC input must be taken

back high again before the next data transfer is initiated.

Serial Data Loading Format (Daisy-Chain Mode)

By connecting DCEN high the daisy-chain mode is enabled.

This mode of operation is designed for multi-DAC systems

where several AD7243s may be connected in cascade (see Fig-

ure 16). In this mode the internal gating circuitry on SCLK is

disabled, and a serial data output facility is enabled. The inter-

nal gating signal is permanently active (low) so that the SCLK

signal is continuously applied to the input shift register when

SYNC is low. The data is clocked into the register on each fall-

ing SCLK edge after SYNC going low. If more than 16 clock

pulses are applied, the data ripples out of the shift register and

appears on the SDO line. By connecting this line to the SDIN

input on the next AD7243 in the chain, a multi-DAC interface

may be constructed. Sixteen SCLK pulses are required for each

DAC in the system. Therefore, the total number of clock cycles

must equal 16N where N is the total number of devices in the

chain. When the serial transfer to all devices is complete, SYNC

should be taken high. This prevents any further data being

clocked into the input register.

A continuous SCLK source may be used if it can be arranged

that SYNC is held low for the correct number of clock cycles.

Alternatively, a burst clock containing the exact number of clock

cycles may be used and SYNC taken high some time later.

When the transfer to all input registers is complete, a common

LDAC signal updates all DAC latches with the lower 12 bits of

data in each input register. All analog outputs are therefore up-

dated simultaneously on the falling edge of LDAC.

Clear Function (CLR)

The clear function bypasses the input shift register and loads the

DAC Latch with all 0s. It is activated by taking CLR low. In all

ranges except the Offset Binary bipolar range (–5 V to +5 V) the

output voltage is reset to 0 V. In the offset binary bipolar range

the output is set to –REFIN. The clear function is especially

useful at power-up as it enables the output to be reset to a

known state.

SCLK

DB11 (N)

MSB

DB0 (N)

LSB

* = DON'T CARE

SDIN

SYNC

LDAC

CLR

DB0 (N)

LSB

SDO

DB15 (N)*

DB15*

(N + 1)

DB11 (N + 1)

MSB

DB0 (N + 1)

LSB

UNDEFINED

DB15 (N)*

DB11 (N)

MSB

Figure 8. Timing Diagram (Daisy-Chain Mode)

AD7243

–8–

REV. A

APPLYING THE AD7243

Power Supply Decoupling

To achieve optimum performance when using the AD7243, the

and V

lines should each be decoupled to DGND using

0.1 µF capacitors. In noisy environments it is recommended

that 10 µF capacitors be connected in parallel with the 0.1 µF

capacitors.

The internal scaling resistors provided on the AD7243 allow

several output voltage ranges. The part can produce unipolar

output ranges of 0 V to +5 V or 0 V to +10 V and a bipolar out-

put range of ±5 V. Connections for the various ranges are out-

lined below.

Unipolar (0 V to +10 V) Configuration

The first of the configurations provides an output voltage range

of 0 V to +10 V. This is achieved by connecting the output off-

set resistor R

OFS

(Pin 13) to AGND. Natural Binary data format

is selected by connecting BIN/COMP (Pin 4) to DGND. In this

configuration, the AD7243 can be operated using either single

or dual supplies. Note that the V

supply must be ≥+14.25 V

for this range in order to maintain sufficient amplifier head-

room. Dual supplies may be used to improve settling time and

give increased current sink capability for the amplifier. Figure 9

shows the connection diagram for unipolar operation of the

AD7243. Table I shows the digital code vs. analog output for

this configuration.

DAC

AGND

DGND

REFOUT

REFIN

OFS

OUT

AD7243*

BIN/

COMP

0V OR V

0V TO + 10V

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 9. Unipolar (0 V to +10 V) Configuration

Table I. Unipolar Code Table (0 V to +10 V Range)

Input Data Word

MSB LSB Analog Output, V

OUT

XXXX 1111 1111 1111 +2 REFIN × (4095/4096)

XXXX 1000 0000 0001 +2 REFIN × (2049/4096)

XXXX 1000 0000 0000 +2 REFIN × (2048/4096) = +REFIN

XXXX 0111 1111 1111 +2 REFIN × (2047/4096)

XXXX 0000 0000 0001 +2 REFIN × (1/4096)

XXXX 0000 0000 0000 0 V

X = Don’t Care.

Note: 1 LSB = 2 REFIN/4096.

Unipolar (0 V to +5 V) Configuration

The 0 V to +5 V output voltage range is achieved by connecting

OFS

to V

OUT

. Once again, the AD7243 can be operated using

either single or dual supplies. The table for output voltage vs.

digital code is as in Table I, with 2REFIN replaced by REFIN.

Note, for this range, 1 LSB = REFIN • (2

–12

) = (REFIN/4096).

Bipolar (ⴞ5 V) Configuration

The bipolar configuration for the AD7243, which gives an out-

put range of –5 V to +5 V, is achieved by connecting R

OFS

REFIN. The AD7243 must be operated from dual supplies to

achieve this output voltage range. Either offset binary or two’s

complement data format may be selected. Figure 10 shows the

connection diagram for bipolar operation. An AD586 provides

the reference voltage for the DAC but this could be provided by

the on-chip reference by connecting REFOUT to REFIN.

DAC

AGND

DGND

REFIN

OFS

2R 2R

AD7243*

BIN/ COMP

–5V TO + 5V

*ADDITIONAL PINS OMITTED FOR CLARITY

AD586

GND

OUT

Figure 10. Bipolar Configuration with External Reference

Bipolar Operation (Two’s Complement Data Format)

The AD7243 is configured for two’s complement data format

by connecting BIN/COMP (Pin 4) high. The analog output vs.

digital code is shown in Table II.

Table II. Two’s Complement Bipolar Code Table

Input Data Word

MSB LSB Analog Output, V

OUT

XXXX 0111 1111 1111 +REFIN × (2047/2048)

XXXX 0000 0000 0001 +REFIN × (1/2048)

XXXX 0000 0000 0000 0 V

XXXX 1111 1111 1111 –REFIN × (1/2048)

XXXX 1000 0000 0001 –REFIN × (2047/2048)

XXXX 1000 0000 0000 –REFIN × (2048/2048) = –REFIN

X = Don’t Care.

Note: 1 LSB = REFIN/2048.

Bipolar Operation (Offset Binary Data Format)

The AD7243 is configured for Offset Binary data format by

connecting BIN/COMP (Pin 4) low. The analog output vs. digi-

tal code may be obtained by inverting the MSB in Table II.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

AD7243BRZ-REEL

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Digital to Analog Converters - DAC CMOS 12B SERIAL IC

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AD7243BRZ-REEL

AD7243BRZ-REEL

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