M41T256YMH7E Datasheet M41T256YMH7E, M41T256YMH7F | P10-P12

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Operating modes M41T256Y

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2.1.2 Start data transfer

A change in the state of the data line, from high to low, while the clock is high, defines the

START condition.

2.1.3 Stop data transfer

A change in the state of the data line, from low to high, while the clock is high, defines the

STOP condition.

2.1.4 Data valid

The state of the data line represents valid data when after a start condition, the data line is

stable for the duration of the high period of the clock signal. The data on the line may be

changed during the Low period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a start condition and terminated with a stop condition.

The number of data bytes transferred between the start and stop conditions is not limited.

The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.

By definition a device that gives out a message is called “transmitter,” the receiving device

that gets the message is called “receiver.” The device that controls the message is called

“master.” The devices that are controlled by the master are called “slaves.”

2.1.5 Acknowledge

Each byte of eight bits is followed by one acknowledge clock pulse. This acknowledge clock

pulse is a low level put on the bus by the receiver whereas the master generates an extra

acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate

an acknowledge after the reception of each byte that has been clocked out of the slave

transmitter.

The device that acknowledges has to pull down the SDA line during the acknowledge clock

pulse in such a way that the SDA line is a stable Low during the High period of the

acknowledge related clock pulse. Of course, setup and hold times must be taken into

account. A master receiver must signal an end of data to the slave transmitter by not

generating an acknowledge on the last byte that has been clocked out of the slave. In this

case the transmitter must leave the data line High to enable the master to generate the

STOP condition.

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M41T256Y Operating modes

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Figure 4. Serial bus data transfer sequence

Figure 5. Acknowledgement sequence

AI04756

(SDA) DATA

(SCL) CLOCK

DATA LINE

STABLE

DATA VALID

START

CONDITION

CHANGE OF

DATA ALLOWED

STOP

CONDITION

AI00601

DATA OUTPUT

BY RECEIVER

DATA OUTPUT

BY TRANSMITTER

SCL FROM

MASTER

START

CLOCK PULSE FOR

ACKNOWLEDGEMENT

12 89

MSB LSB

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Operating modes M41T256Y

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Figure 6. Bus timing requirements sequence

Table 2. AC characteristics

2.2 Read mode

In this mode the master reads the M41T256Y slave after setting the slave address (see

Figure 7 on page 13). Following the WRITE mode control bit (R/W

=0) and the Acknowledge

Bit, the byte addresses A(0) and A(1) are written to the on-chip address pointer (MSB of

address byte A(0) is a “Don’t care”). Next the START condition and slave address are

repeated followed by the READ mode control bit (R/W

=1). At this point the master

transmitter becomes the master receiver. The data byte which was addressed will be

transmitted and the master receiver will send an acknowledge bit to the slave transmitter.

The address pointer is only incremented on reception of an acknowledge clock. The

M41T256Y slave transmitter will now place the data byte at address An+1 on the bus, the

Symbol Parameter

(1)

1. Valid for ambient operating temperature: T

= –25 to 70°C; V

= 4.5 to 5.5V (except where noted).

Min Max Unit

SCL

SCL clock frequency 0 400 kHz

BUF

Time the bus must be free before a new transmission can

start

1.3 µs

SDA and SCL fall time 300 ns

HD:DAT

Data hold time 0 µs

HD:STA

START condition hold time

(after this period the first clock pulse is generated)

600 ns

HIGH

Clock high period 600 ns

LOW

Clock low period 1.3 µs

SDA and SCL rise time 300 ns

SU:DAT

(2)

2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL

Data setup time 100 ns

SU:STA

START condition setup time

(only relevant for a repeated start condition)

600 ns

SU:STO

STOP condition setup time 600 ns

AI00589

SDA

tSU:STOtSU:STA

tHD:STA

SCL

tSU:DAT

tHD:DAT

tHIGH

tLOW

tHD:STAtBUF

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M41T256YMH7E

Mfr. #:

Buy M41T256YMH7E

Manufacturer:

STMicroelectronics

Description:

Real Time Clock Serial 256K (32Kx8)

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New from this manufacturer.

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M41T256YMH7E

M41T256YMH7E

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