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Operating modes M41T256Y
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2.5 Sleep mode
In order to minimize the battery current draw while in storage, the M41T256Y provides the
user with a battery “sleep mode,” which disconnects the RAM memory array from the
external Lithium battery normally used to provide non-volatile operation in the absence of
V
CC
. This can significantly extend the lifetime of the battery, when non-volatile operation is
not needed.
Note: The sleep mode will remove power from the RAM array only and not affect the data retention
of the TIMEKEEPER Registers (7FF0h through 7FFFh - this includes the Calibration
Register).
The sleep mode (SLP) Bit located in register 7FF8h (D6), must be set to a '1' by the user
while the device is powered by V
CC
. This will “arm” the sleep mode latch, but not actually
disconnect the RAM array from power until the next power-down cycle. This protects the
user from immediate data loss in the event he inadvertently sets the SLP Bit. Once V
CC
falls
below V
SO
(V
BAT
), the sleep mode circuit will be engaged and the RAM array will be isolated
from the battery, resulting in both a lower battery current, and a loss of RAM data.
Note: Upon initial battery attach or initial power application without the battery, the state of the SLP
Bit will be undetermined. Therefore, the SLP Bit should be initialized to '0' by the user.
Additional current reduction can be achieved by setting the STOP (ST) Bit in register 7FF9h
(D7), turning off the clock oscillator. This combination will result in the longest possible
battery life, but also loss of time and data. When the device is again powered-up, the user
should first read the SLP Bit to determine if the device is currently in sleep mode, then reset
the bit to '0' in order to disable the sleep mode (this will NOT be automatically taken care of
during the power-up).
Note: See AN1570, “M41T256Y Sleep Mode Function” for more information on sleep mode and
battery lifetimes.
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M41T256Y Clock operation
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3 Clock operation
Year, month, and date are contained in the last three registers of the TIMEKEEPER
®
register map (see Table 3 on page 18). Bits D0 through D2 of the next register contain the
day (day of week). Finally, there are the registers containing the seconds, minutes, and
hours, respectively. The first clock register is the control register (this is described in the
clock calibration section).
The nine clock registers may be read one byte at a time, or in a sequential block. The control
register (Address location 7FF8h) may be accessed independently. Provision has been
made to assure that a clock update does not occur while any of the nine clock addresses
are being read. If a clock address is being read, an update of the clock registers will be
halted. This will prevent a transition of data during the read.
3.1 Reading the clock
The nine byte clock register (see Table 3 on page 18) is used to both set the clock and to
read the date and time from the clock, in a binary coded decimal format. The system-to-user
transfer of clock data will be halted whenever the address being read is a clock address
(7FF9h to 7FFFh). The update will resume either due to a stop condition or when the pointer
increments to a RAM address.
This prevents reading data in transition. The TIMEKEEPER
®
cells in the register map are
only data registers and not actual clock counters, so updating the registers can be halted
without disturbing the clock itself.
3.2 Setting the clock
Bit D7 of the control register (7FF8h) is the write clock bit. Setting the write clock bit to a '1'
will allow the user to write the desired day, date, and time data in 24-hour BCD format.
Resetting the write clock bit to a '0' then transfers the values of all time registers (7FF8h-
7FFFh) to the actual clock counters and resets the internal divider (or clock) chain.
Note: The tenths/hundredths of seconds register will automatically be reset to zero when the
WRITE clock bit is set.
Other register bits such as FT, TEB, and ST may be written without setting the WC Bit. In
such cases, the clock data will be undisturbed and will retain their previous values.
3.3 Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant
amount of time on the shelf, the oscillator can be turned off to minimize current drain on the
battery. The stop bit (ST) is the most significant bit of the seconds register. Setting it to '1'
stops the oscillator. Setting it to '0' restarts the oscillator in approximately one second.
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Clock operation M41T256Y
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Table 3. TIMEKEEPER
®
register map
Keys:
S = Sign bit
FT = Frequency test bit
ST = Stop bit
WC = Write clock bit
X = '1' or '0'
BL = Battery low flag (read only bit)
TB = Tamper bit (read only bit)
TEB = Tamper enable bit
0 = Must be set to '0'
SLP = Sleep mode bit
Note: 7FF0h through 7FF6h are invalid addresses and when read will return arbitrary data.
3.4 Power-on reset
The M41T256Y continuously monitors V
CC
. When V
CC
falls to the power fail detect trip
point, the RST
pulls low (open drain) and remains low on power-up for t
REC
after V
CC
passes V
PFD
(max). The RST pin is an open drain output and an appropriate pull-up resistor
should be chosen to control rise time.
Address
Data
Function/Range
BCD Format
D7 D6 D5 D4 D3 D2 D1 D0
7FFFh 10 years Year Year 00-99
7FFEh 0 0 0 10M Month Month 01-12
7FFDh 0 0 10 date Date: Day of Month Date 01-31
7FFCh BL FT TEB TB 0 Day of Week Tamper/day 0-1/01-07
7FFBh 0 0
10 hours
Hours (24 Hour Format) Hours 00-23
7FFAh 0 10 minutes Minutes Minutes 00-59
7FF9h ST 10 seconds Seconds Seconds 00-59
7FF8h WC SLP S Calibration Control
7FF7h 0.1 Seconds 0.01 Seconds Seconds 00-99
7FF6hXXXXXXXXReserved
7FF5hXXXXXXXXReserved
7FF4hXXXXXXXXReserved
7FF3hXXXXXXXXReserved
7FF2hXXXXXXXXReserved
7FF1hXXXXXXXXReserved
7FF0hXXXXXXXXReserved
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M41T256YMH7F

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
IC RTC CLK/CALENDAR I2C 44-SOH
Lifecycle:
New from this manufacturer.
Delivery:
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