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M41T256Y Summary
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Figure 1. Logic diagram
1. For 44-pin SNAPHAT (MT) package only.
Table 1. Signal names
FT Frequency test (open drain)
RST Reset output (open drain)
SCL Serial clock input
SDA Serial data input/output
V
CC
Supply voltage
V
SS
Ground
TP Tamper input
AI04754b
SCL
V
CC
M41T256Y
V
SS
SDA
TP
FT
RST
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Summary M41T256Y
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Figure 2. 44-pin SOIC (MH - snaphat)
Figure 3. Block diagram
1. Open drain output
22
44
43
1
M41T256Y
10
2
5
6
7
8
9
11
12
13
14
15
21
40
39
36
35
34
33
32
31
30
29
28
3
4
38
37
42
41
16
17
18
19
20
27
26
25
24
23
NC
NC
NF
NF
NF
NF
NF
NF
NF
NF
NF
NF
NF
NF
NF
NF
NF
NF
NF
NF
NF
NF
NF
NF
TP
NC
NF
RST
SDA
V
SS
V
SS
NC
V
SS
V
CC
NC
FT
NC
NC
NF
SCL
NC
NC
NC
NC
AI07022
AI04759
COMPARE
V
PFD
= 4.38V
V
CC
COMPARE
V
SO
= V
BAT
POWER
V
BL
= 2.5V
BL
COMPARE
Crystal
I
2
C
INTERFACE
REAL TIME CLOCK
CALENDAR
32,752 BYTES
USER RAM
RTC
& CALIBRATION
TAMPER BIT
SDA
SCL
POR
RST
(1)
TP
V
BAT
32KHz
OSCILLATOR
FT
(1)
PULL-UP TO
CHIP V
CC
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M41T256Y Operating modes
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2 Operating modes
The M41T256Y clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 256K bytes
contained in the device can then be accessed sequentially in the following order:
0-7FEF = General purpose RAM
7FF0-7FF6 = Reserved
7FF7h = Tenths/hundredths register
7FF8h = Control register
7FF9h = Seconds register
7FFAh = Minutes register
7FFBh = Hour register
7FFCh = Tamper/day register
7FFDh = Date register
7FFEh = Month register
7FFFh = Year register
The M41T256Y clock continually monitors V
CC
for an out-of tolerance condition. Should
V
CC
fall below V
PFD
, the device terminates an access in progress and resets the device
address counter. Inputs to the device will not be recognized at this time to prevent
erroneous data from being written to the device from an out-of-tolerance system. When V
CC
falls below V
SO
, the device automatically switches over to the battery and powers down into
an ultra low current mode of operation to conserve battery life. As system power returns and
V
CC
rises above V
SO
, the battery is disconnected, and the power supply is switched to
external V
CC
. Write protection continues until V
CC
reaches V
PFD
plus t
REC
.
For more information on Battery Storage Life refer to Application Note AN1012.
2.1 2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a
bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must
be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is high.
Changes in the data line, while the clock line is high, will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
2.1.1 Bus not busy
Both data and clock lines remain High.
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M41T256YMH7F

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
IC RTC CLK/CALENDAR I2C 44-SOH
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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