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96D4-32G2666ER-AT

P1-P3P4-P6P7-P9P10-P12
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2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com
Tel. (408) 732-5000 Fax (408) 732-5055
Page 10 of 12
IDD SPECIFICATION PARAMETER & POWER CONSUMPTION (PART2 OF 2)
(Values are for the DDR4 SDRAM only and are computed from values specified in the vendor’ s component data sheet)
Symbol Proposed Conditions Value Units
IDD4W
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: High between WR;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: seamless write data burst with different
data between one burst and the next one ; DM_n: stable at 1; Bank Activity: all banks open, WR commands cycling through banks:
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at HIGH; Pattern Details: Refer to
Component Datasheet for detail pattern
2,710
mA
IDD5B
Burst Refresh Current (1X REF)
CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: High
between REF; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: VDDQ; DM_n: stable at
1; Bank Activity: REF command every nRFC ; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern
Details: Refer to Component Datasheet for detail pattern
4,730
mA
IPP5B
Burst Refresh Write IPP Current (1X REF)
Same condition with IDD5B
378
mA
IDD6N
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Low Power Array Self Refresh (LP ASR) : Normal4; CKE: Low; External clock: Off; CK_t and CK_c#: LOW; CL:
Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address,
Data IO: High; DM_n: stable at 1; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT
Signal: MID-LEVEL
890
mA
IDD6E
Self-Refresh Current: Extended Temperature Range)
TCASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Extended4; CKE: Low; External clock: Off; CK_t and CK_c: LOW; CL:
Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n, Command, Address, Bank Group Address, Bank Address,
Data IO: High; DM_n:stable at 1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in
Mode Registers2; ODT Signal: MID-LEVEL
1,250
mA
IDD6R
Self-Refresh Current: Reduced Temperature Range
TCASE: 0 - TBD (~35-45)°C; Low Power Array Self Refresh (LP ASR) : Reduced4; CKE: Low; External clock: Off; CK_t and CK_c#:
LOW; CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank
Address, Data IO: High; DM_n:stable at 1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT:
Enabled in Mode Registers2; ODT Signal: MID-LEVEL
640
mA
IDD6A
Auto Self-Refresh Current
TCASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Auto4;Partial Array Self-Refresh (PASR): Full Array; CKE: Low;
External clock: Off; CK_t and CK_c#: LOW; CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n#, Command,
Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Auto Self-Refresh operation; Output
Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL
840
mA
IDD7
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern; BL:
81; AL: CL-1; CS_n: High between ACT and RDA; Command, Address, Bank Group Address, Bank Address Inputs: partially
toggling ; Data IO: read data bursts with different data between one burst and the next one ; DM_n: stable at 1; Bank Activity: two
times interleaved cycling through banks (0, 1, ...7) with different addressing; Output Buffer and RTT: Enabled in Mode Registers2;
ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
4,790
mA
IPP7
Operating Bank Interleave Read IPP Current
Same condition with IDD7
216
mA
IDD8
Maximum Power Down Current
405
mA
PDIMM
Power Consumption per DIMM
System is operating at 1067MHz clock with VDD = 1.2V. This parameter is calculated at a common loading.
5,748
mW
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!
!
2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com
Tel. (408) 732-5000 Fax (408) 732-5055
Page 11 of 12
TIMING PARAMETER
Note:
1. Unit ’nCK’ represents one clock cycle of the input clock, counting the actual clock edges.
Parameter
Symbol
DDR4-2666
Units
Min Max
Clock cycle time at CL=17, CWL=12 tCK 0.75 <0.833
ns
Internal read command to first data tAA 14.25 18 ns
ACT to internal read or write delay time tRCD 14.25 ns
PRE command period tRP 14.25 ns
ACT to ACT or REF command period tRC 46.25 ns
ACTIVE to PRECHARGE command period tRAS 32 9*tREFI ns
Average clock high pulse width tCH(avg) 0.48 0.52 tCK
Average clock low pulse width tCL(avg) 0.48 0.52 tCK
DQS,
DQS
to DQ skew, per group, per access
tDQSQ - 0.18
ps
DQ output hold time from DQS,
DQS
tQH 0.74 -
tCK
DQ low-impedance time from CK,
CK
tLZ(DQ) -310 170
ps
DQ high-impedance time from CK,
CK
tHZ(DQ) - 170
ps
DQS,
DQS
READ Preamble
tRPRE 0.9 TBD
tCK
DQS,
DQS
differential READ Postamble
tRPST 0.33 TBD
tCK
DQS,
DQS
output high time
tQSH 0.4 -
tCK
DQS,
DQS
output low time
tQSL 0.4 -
tCK
DQS,
DQS
WRITE Preamble
tWPRE 0.9 -
tCK
DQS,
DQS
WRITE Postamble
tWPST 0.33 TBD
tCK
DQS,
DQS
low-impedance time (Referenced from RL-1)
tLZ(DQS) -310 170
ps
DQS,
DQS
high-impedance time (Referenced from RL+BL/2)
tHZ(DQS) - 170
ps
DQS,
DQS
differential input low pulse width
tDQSL 0.46 0.54
tCK
DQS,
DQS
differential input high pulse width
tDQSH 0.46 0.54
tCK
DQS,
DQS
rising edge to CK,
CK
rising edge
tDQSS -0.27 0.27
tCK
DQS,
DQS
falling edge setup time to CK,
CK
rising edge
tDSS 0.18 -
tCK
DQS,
DQS
falling edge hold time to CK,
CK
rising edge
tDSH 0.18 -
tCK
DLL locking time tDLLK
854 -
nCK
1
Internal READ Command to PRECHARGE Command delay tRTP max(4nCK,7.5ns) -
Delay from start of internal write trans-action to internal read command for different bank group tWTR_S max(2nCK,2.5ns) -
Delay from start of internal write trans-action to internal read command for same bank group tWTR_L max(4nCK,7.5ns) -
WRITE recovery time tWR 15 - ns
Mode Register Set command cycle time tMRD 8 - nCK
1
Mode Register Set command update delay tMOD max(24nCK,15ns) -
CAS
to
CAS
command delay for same bank group
tCCD_L max(5 nCK, 5 ns) -
nCK
1
CAS
to
CAS
command delay for different bank group
tCCD_S 4
Auto precharge write recovery + precharge time tDAL tWR + roundup (tRP / tCK) nCK
1
Multi-Purpose Register Recovery Time tMPRR 1 - nCK
1
ACTIVE to ACTIVE command delay to same bank group for 1KB page size tRRD max(4nCK,4.9ns) -
Four activate window for 1KB page size tFAW max(20nCK,21ns) -
Command and Address setup time to CK,
CK
referenced to Vih(ac) / Vil(ac) levels
tIS(base) TBD -
ps
Command and Address hold time from CK,
CK
referenced to Vih(ac) / Vil(ac) levels
tIH(base) TBD -
ps
Power-up and RESET calibration time tZQinit 1024 - nCK
1
Normal operation Full calibration time tZQoper 512 - nCK
1
Normal operation short calibration time tZQCS 128 - nCK
1
Exit Reset from CKE HIGH to a valid command
tXPR
max (5nCK,tRFC(min)+
10ns)
-
nCK
1
Exit Power Down with DLL on to any valid command; Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
tXP max(4nCK,6ns) -
nCK
1
Asynchronous RTT turn-on delay (Power-Down with DLL frozen) tAONAS 1 9 ns
Asynchronous RTT turn-off delay (Power-Down with DLL frozen) tAOFAS 1 9 ns
RTT dynamic change skew tADC 0.3 0.7 tCK
8Gb REFRESH to REFRESH OR REFRESH to ACTIVE command interval tRFC 350 - ns
Average periodic refresh interval (0°C ≤ TCASE ≤ 85 °C) tREFI 7.8 7.8 us
Average periodic refresh interval (85°C ≤ TCASE ≤ 95 °C) tREFI 3.9 3.9 us
Exit Self Refresh to commands not requiring a locked DLL tXS tRFC(min)+10ns -
Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK(min) - nCK
1
Power Down Entry to Exit Timing tPD tCKE(min) 9*tREFI tCK
Write leveling output delay tWLO 0 9.5 ns
Write leveling output error tWLOE 0 2 ns
A
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4
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!
!
2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com
Tel. (408) 732-5000 Fax (408) 732-5055
Page 12 of 12
PHYSICAL DIMENSIONS (UNITS IN INCHES)
(Drawing not to scale)
Back
Note: Tolerance on all dimensions ±0.15mm unless otherwise noted
Disclaimer:
No part of this document may be copied or reproduced in any form or by any means, or transferred to any third party,
without the prior written consent of an authorized representative of ATP Electronics (“ATP”). The information in this
document is subject to change without notice. ATP assumes no responsibility for any errors or omissions that may appear
in this document, and disclaims responsibility for any consequences resulting from the use of the information set forth
herein. ATP makes no commitments to update or to keep current information contained in this document. The
information set forth in this document is considered to be “Proprietary” and “Confidential” property owned by ATP.
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P1-P3P4-P6P7-P9P10-P12

96D4-32G2666ER-AT

Mfr. #:
Buy 96D4-32G2666ER-AT
Manufacturer:
Advantech
Description:
Memory Modules 32G DDR4 2666 288PIN 2GX4 REG 1.2V SAM
Lifecycle:
New from this manufacturer.
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