OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

96D4-32G2666ER-AT

P1-P3P4-P6P7-P9P10-P12
A
A
T
T
P
P
A
A
4
4
B
B
3
3
2
2
Q
Q
B
B
4
4
B
B
N
N
T
T
D
D
S
S
E
E
Y
Y
o
o
u
u
r
r
U
U
l
l
t
t
i
i
m
m
a
a
t
t
e
e
M
M
e
e
m
m
o
o
r
r
y
y
S
S
o
o
l
l
u
u
t
t
i
i
o
o
n
n
!
!
2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com
Tel. (408) 732-5000 Fax (408) 732-5055
Page 7 of 12
FUNCTIONAL BLOCK DIAGRAM (PART3 OF 3)
Note 1
Unless otherwise noted, resistor values are 15± 5%.
Note 2 See the Net Structure diagrams for all resistors associated with the command, address and control
bus.
Note 3 ZQ resistors are 240 ± 1%. For all other resistor values refer to the appropriate wiring diagram.
Note 4 DRAM TEN pin need to be tied to Vss.
Note 5 VDDSPD also connects to the register (RCD).
Note 6 VREFCA from the edge connector only connects with the register (RCD). The RCD sources a
separate VREFCA to all the SDRAMs.
A
A
T
T
P
P
A
A
4
4
B
B
3
3
2
2
Q
Q
B
B
4
4
B
B
N
N
T
T
D
D
S
S
E
E
Y
Y
o
o
u
u
r
r
U
U
l
l
t
t
i
i
m
m
a
a
t
t
e
e
M
M
e
e
m
m
o
o
r
r
y
y
S
S
o
o
l
l
u
u
t
t
i
i
o
o
n
n
!
!
2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com
Tel. (408) 732-5000 Fax (408) 732-5055
Page 8 of 12
ABSOLUTE MAXIMUM DC RATINGS
Item Symbol Rating Units Notes
Voltage on V
DD
pin relative to V
SS
V
DD
-0.4V ~ 1.5V V 1,3
Voltage on V
DDQ
pin relative to V
SS
V
DDQ
-0.4V ~ 1.5V V 1,3
Voltage on V
PP
pin relative to V
SS
V
PP
-0.4V ~ 3.0V V 4
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-0.4V ~ 1.975V V 1
Storage Temperature T
STG
-55 to +100
o
C 1,2
Operating Temperature T
CASE
0 to +95
o
C 1,2
Note:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300 mV of each other at all times;and VREFCA must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500 mV;
VREFCA may be equal to or less than 300 mV
4. VPP must be equal or greater than VDD/VDDQ at all times.
AC & DC OPERATING CONDITIONS
Recommended operating conditions
Item Symbol Min. Typical Max. Units
Supply Voltage
1
,
2
,
3
V
DD
1.14 1.2 1.26 V
Supply Voltage for Output
1
,
2
,
3
V
DDQ
1.14 1.2 1.26 V
DRAM Activating Power Supply
3
V
PP
2.375 2.5 2.75 V
Input reference voltage command/
address bus
V
REFCA(DC) TBD TBD TBD V
Termination reference voltage (DC) –
command/address bus
4
V
TT
0.49 * V
DD
-
20mA
0.50 * V
DD
0.51 * V
DD
+
20mA
V
Input High Voltage (DC) V
IH
(DC) TBD - TBD V
Input Low Voltage (DC) V
IL
(DC) TBD - TBD V
Input High Voltage (AC) V
IH
(AC) TBD - - V
Input Low Voltage (AC) V
IL
(AC) - - TBD V
Note:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. DC bandwidth is limited to 20MHz.
4. VTT termination voltages in excess of specification limit will adversely affect command and address signals' voltage margins, and reduce timing margins.
RELIABILITY
MTBF @25
o
C
(Hours)
1
FIT @ 25
o
C
2
MTBF @40
o
C (Hours)
1
FIT @ 40
o
C
2
1,783,000 391 987,100 758
Note:
1. The Mean Time between Failures (MTBF) is calculated using a prediction methodology, Bellcore Prediction, which based on reliability data of the individual
components in the module. It assumes nominal voltage, with all other parameters within specified range.
2. Failures per Billion Device-Hours
A
A
T
T
P
P
A
A
4
4
B
B
3
3
2
2
Q
Q
B
B
4
4
B
B
N
N
T
T
D
D
S
S
E
E
Y
Y
o
o
u
u
r
r
U
U
l
l
t
t
i
i
m
m
a
a
t
t
e
e
M
M
e
e
m
m
o
o
r
r
y
y
S
S
o
o
l
l
u
u
t
t
i
i
o
o
n
n
!
!
2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com
Tel. (408) 732-5000 Fax (408) 732-5055
Page 9 of 12
IDD SPECIFICATION PARAMETER & POWER CONSUMPTION (PART1 OF 2)
(Values are for the DDR4 SDRAM only and are computed from values specified in the vendor’ s component data sheet)
Symbol Proposed Conditions Value Units
IDD0
Operating One Bank Active-Precharge Current (AL=0)
CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: High
between ACT and PRE; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling; Data IO: VDDQ; DM_n:
stable at 1; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode
Registers2; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
1,510 mA
IPP0
Operating One Bank Active-Precharge IPP Current
Same condition with IDD0
126
mA
IDD1
Operating One Bank Active-Read-Precharge Current (AL=0)
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n:
High between ACT, RD and PRE; Command, Address, Bank Group Address, Bank Address Inputs, Data IO: partially toggling;
DM_n: sta-ble at 1; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode
Registers2; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
1,903
mA
IDD2N
Precharge Standby Current (AL=0)
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: VDDQ; DM_n: stable at 1; Bank
Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: Refer to
Component Datasheet for detail pattern
1,300
mA
IDD2NT
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: VSSQ; DM_n: stable at 1; Bank
Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: toggling according ; Pattern Details:
Refer to Component Datasheet for detail pattern
1,400
mA
IDD2P
Precharge Power-Down Current
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1;
Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0
730
mA
IDD2Q
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1;
Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1;Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0
1,230
mA
IDD3N
Active Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: VDDQ; DM_n: stable at 1;Bank
Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details:Refer to
Component Datasheet for detail pattern
1,760
mA
IPP3N
Active Standby IPP Current
Same condition with IDD3N
108
mA
IDD3P
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: sRefer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1;
Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all
banks open; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0
880
mA
IDD4R
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 82; AL: 0; CS_n: High between RD;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: seamless read data burst with different
data between one burst and the next one according ; DM_n: stable at 1; Bank Activity: all banks open, RD commands cycling
through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: Refer
to Component Datasheet for detail pattern
2,830
mA
P1-P3P4-P6P7-P9P10-P12

96D4-32G2666ER-AT

Mfr. #:
Buy 96D4-32G2666ER-AT
Manufacturer:
Advantech
Description:
Memory Modules 32G DDR4 2666 288PIN 2GX4 REG 1.2V SAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet