Data Sheet ADCMP391
THEORY OF OPERATION
BASIC COMPARATOR
In its most basic configuration, a comparator can be used to
convert an analog input signal to a digital output signal (see
Figure 19). The analog signal on IN+ is compared to the voltage
on IN, and the voltage at OUT is either high or low, depending
on whether IN+ is at a higher or lower potential than IN−,
respectively.
Figure 19. Basic Comparator and Input and Output Signals
RAIL-TO-RAIL INPUT (RRI)
Using a CMOS nonRRI stage (that is, a single differential pair)
limits the input voltage to approximately one gate-to-source
voltage (V
GS
) away from one of the supply lines. Because V
GS
for
normal operation is commonly more than 1 V, a single differential
pair input stage comparator greatly restricts the allowable input
voltage. This restriction can be quite limiting with low voltage
supplies. To resolve this issue, RRI stages allow the input signal
range to extend up to the supply voltage range. In the case of the
ADCMP391, the inputs continue to operate 200 mV beyond the
supply rails.
OPEN-DRAIN OUTPUT
The ADCMP391 has an open-drain output stage that requires
an external resistor to pull up to the logic high voltage level
when the output transistor is switched off. The pull-up resistor
must be large enough to avoid excessive power dissipation, but
small enough to switch logic levels reasonably quickly when the
comparator output is connected to other digital circuitry. The
rise time of the open-drain output depends on the pull-up
resistor (R
PULLUP
) and load capacitor (C
L
) used.
The rise time can be calculated by
t
R
= 2.197 R
PULLUP
C
L
(1)
POWER-UP BEHAVIOR
On power-up, when V
CC
reaches 0.9 V, t h e ADCMP391 is
guaranteed to assert an output low logic. When the voltage on
the V
CC
pin exceeds UVLO, the comparator inputs take control.
CROSSOVER BIAS POINT
Rail-to-rail inputs of this type of architecture, in both op amps
and comparators, have a dual front-end design. PMOS devices
are inactive near the V
CC
rail, and NMOS devices are inactive near
GND. At some predetermined point in the common-mode range, a
crossover occurs. At this point, normally 0.8 V and V
CC
0.8 V, the
measured offset voltages change.
COMPARATOR HYSTERESIS
In noisy environments, or when the differential input amplitudes
are relatively small or slow moving, adding hysteresis (V
HYST
) to
the comparator is often desirable. The transfer function for a
comparator with hysteresis is shown in Figure 20. As the input
voltage approaches the threshold (0 V in Figure 20) from below
the threshold region in a positive direction, the comparator
switches from low to high when the input crosses +V
HYST
/2. The
new switch threshold becomes −V
HYST
/2. The comparator remains
in the high state until the −V
HYST
/2 threshold is crossed from
below the threshold region in a negative direction. In this
manner, noise or feedback output signals centered on the 0 V
input cannot cause the comparator to switch states unless it
exceeds the region bounded by ±V
HYST
/2.
Figure 20. Comparator Hysteresis Transfer Function
OUT
V
IN
V
REF
IN+
IN–
V
CC
V+
V+
V
REF
V
IN
V
OUT
0V
t
12206-019
OUTPUT
INPUT
0V
V
OL
V
OH
+V
HYST
2
–V
HYST
2
12206-020
Rev. 0 | Page 9 of 15
ADCMP391 Data Sheet
TYPICAL APPLICATIONS
ADDING HYSTERESIS
To add hysteresis, see Figure 21; two resistors are used to create
different switching thresholds, depending on whether the input
signal is increasing or decreasing in magnitude. When the input
voltage increases, the threshold is above V
REF
, and when the
input voltage decreases, the threshold is below V
REF
.
Figure 21. Noninverting Comparator Configuration with Hysteresis
The upper input threshold level is given by
R2
R2R1V
V
REF
IN_HI
)( +
=
(2)
Assuming R
LOAD
>> R2, R
PULLUP
.
The lower input threshold level is given by
( )
PULLUP
CC
PULLUPREF
LOIN
RR2
R1VRR2R1V
V
+
++
=
_
(3)
The hysteresis is the difference between these voltages levels.
PULLUP
CC
IN
RR2
R1V
ΔV
+
=
(4)
WINDOW COMPARATOR FOR POSITIVE VOLTAGE
MONITORING
When monitoring a positive supply, the desired nominal
operating voltage for monitoring is denoted by V
M
, I
M
is the
nominal current through the resistor divider, V
OV
is the
overvoltage trip point, and V
UV
is the undervoltage trip point.
Figure 22. Positive Undervoltage/Overvoltage Monitoring Configuration
Figure 22 illustrates the positive voltage monitoring input
connection. Three external resistors, R
X
, R
Y
, and R
Z
, divide the
positive voltage for monitoring, V
M
, into the high-side voltage,
V
PH
, and the low-side voltage, V
PL
. The high-side voltage is
connected to the IN+ pin of U1 and the low-side voltage is
connected to the INpin of U2.
To trigger an overvoltage condition, the low-side voltage (in this
case, V
PL
) must exceed the V
REF
threshold on the IN+ pin of U2.
Calculate the low-side voltage, V
PL
, by the following:
++
==
Z
YX
Z
OV
REFPL
RRR
R
VVV
(5)
In addition,
R
X
+ R
Y
+ R
Z
= V
M
/I
M
(6)
Therefore, R
Z
, which sets the desired trip point for the
overvoltage monitor, is calculated as
( )
( )
( )
( )
M
OV
MREF
Z
IV
VV
R =
(7)
To trigger the undervoltage condition, the high-side voltage,
V
PH
, must be less than the V
REF
threshold on the INpin of U1.
The high-side voltage, V
PH
, is calculated by
++
+
==
Z
Y
X
Z
Y
UVREFPH
RRR
RR
VVV
(8)
Because R
Z
is already known, R
Y
can be expressed as
( )
( )
( )
( )
Z
MUV
MREF
Y
R
IV
VV
R =
(9)
When R
Y
and R
Z
are known, R
X
can be calculated by
R
X
= (V
M
/I
M
) R
Y
R
Z
(10)
If V
M
, I
M
, V
OV
, or V
UV
changes, each step must be recalculated.
OUT
IN+
IN–
V
REF
= 2.5V
V
IN
V
CC
= 5V
R1
R
LOAD
R
PULLUP
R2
V
OUT
V
IN
V
IN_LO
V
IN_HI
12206-030
OUT1
IN+
IN–
V
REF
OUT2
U1
U2
IN+
IN–
V
M
R
Z
R
Y
R
X
V
PL
V
PH
12206-021
Rev. 0 | Page 10 of 15
Data Sheet ADCMP391
WINDOW COMPARATOR FOR NEGATIVE VOLTAGE
MONITORING
Figure 23 shows the circuit configuration for negative supply
voltage monitoring. To monitor a negative voltage, a reference
voltage is required to connect to the end node of the voltage
divider circuit, in this case, V
REF
.
Figure 23. Negative Undervoltage/Overvoltage Monitoring Configuration
Equation 7, Equation 9, and Equation 10 need some minor
modifications for use with negative voltage monitoring. The
reference voltage, V
REF
, is added to the overall voltage drop;
therefore, it must be subtracted from V
M
, V
UV
, and V
OV
before
using each of them in Equation 7, Equation 9, and Equation 10.
To monitor a negative voltage level, the resistor divider circuit
divides the voltage differential level between V
REF
and the negative
supply voltage into the high-side voltage, V
NH
, and the low-side
voltage, V
NL
. The high-side voltage, V
NH
, is connected to IN+ of
U1, and the low-side voltage, V
NL
, is connected to INof U2.
To trigger an overvoltage condition, the monitored voltage must
exceed the nominal voltage in terms of magnitude, and the
high-side voltage (in this case, V
NH
) on the IN+ pin of U1 must
be more negative than ground. Calculate the high-side voltage,
V
NH
, with the following formula:
( )
OV
Z
YX
Y
X
OV
REFNH
V
RR
R
R
R
VVGND
V +
++
+
==
(11)
In addition,
( )
M
REFM
Z
YX
I
VV
RRR
=++
(12)
Therefore, R
Z
, which sets the desired trip point for the
overvoltage monitor, is calculated by
( )
( )
REF
OV
M
REFMREF
Z
VVI
VV
V
R
=
(13)
To trigger an undervoltage condition, the monitored voltage
must be less than the nominal voltage in terms of magnitude,
and the low-side voltage (in this case, V
NL
) on the IN pin of U2
must be more positive than ground. Calculate the low-side
voltage, V
NL
, by the following:
( )
UV
Z
YX
X
UVREFNL
V
RRR
R
VVGNDV +
++
==
(14)
Because R
Z
is already known, R
Y
can be expressed as follows:
(
)
( )
Z
REF
UVM
REFM
REF
Y
R
V
V
I
V
VV
R
=
(15)
When R
Y
and R
Z
are known, R
X
is then calculated by
( )
Z
Y
M
REFM
X
RR
I
VV
R
=
(16)
PROGRAMMABLE SEQUENCING CONTROL CIRCUIT
The circuit shown in Figure 24 is used to control the power supply
sequencing. The delay is set by the combination of the pull-up
resistor (R
PULLUP
), the load capacitor (C
L
), and the resistor
divider network.
Figure 24. Programmable Sequencing Control Circuit
Figure 25 shows a simplified block diagram for the
programmable sequencing control circuit. The application
delays the enable signal, EN, of the external regulators (LDO x)
in a linear order when the open-drain signal (SEQ) changes
from low to high impedance.
The ADCMP391 has a defined output state during startup, which
prevents any regulator from turning on if V
CC
is still below the
UVLO threshold.
Figure 25. Simplified Block Diagram of a Programmable
Sequencing Control Circuit
OUT1
IN+
V
REF
IN–
OUT2
U1
U2
IN+
IN–
R
X
R
Y
R
Z
V
NL
V
NH
V
M
12206-022
OUT4
OUT3
OUT2
OUT1
R2
V2
R3
V3
R4
V4
R5
R1
V1
R
PULLUP
V
REF
/V
CC
C
L
SEQ
12206-125
U1
U2
U3
U4
IN
EN
OUT
GND
LDO 1
3.0V3.3V
IN
EN
OUT
GND
LDO 2
1.8V
IN
EN
OUT
GND
LDO 3
2.5V
IN
EN
OUT
GND
LDO 4
1.2V
GND
V
REF
/V
CC
SEQ
t
1
t
2
t
3
t
4
12206-124
Rev. 0 | Page 11 of 15

ADCMP391ARZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Comparators Single Comparator Rail-Rail, Low Power
Lifecycle:
New from this manufacturer.
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