ADCMP391 Data Sheet
Figure 26. Programmable Sequencing Control Circuit Timing Diagram
When the SEQ signal changes from low to high impedance, the
load capacitor, C
L
, starts to charge. The time it takes to charge the
load capacitor to the pull-up voltage (in this case, V
REF
or V
CC
) is the
maximum delay programmable in the circuit. It is recommended
to have the threshold within 10% to 90% of the pull-up voltage.
Calculate the maximum allowable delay by
t
MAX
= t
R
= 2.197 R
PULLUP
C
L
(17)
The delay of each output is changed by changing the threshold
voltage, V1 to V4, when the comparator changes its output state.
To calculate the voltage thresholds for the comparator, use the
following formulas:
=
LPULLUP
1
CR
t
REF
eVV1 1
(18)
=
LPULLUP
CR
t
REF
eVV2
2
1
(19)
=
LPULLUP
CR
t
REF
eVV3
3
1
(20)
=
LPULLUP
4
CR
t
REF
e
VV4 1
(21)
The threshold voltages can come from a voltage reference or a
voltage divider circuit, as shown in Figure 24.
First, determine the allowable current, I
DIV
, flowing through the
resistor divider. After the value for I
DIV
is determined, calculate
R1, R2, R3, R4, and R5 using the following formulas:
R5R4R3R2
R1
I
V
R
DIV
REF
DIV
+++
+=
=
(22)
REF
DIV
V
V1R
R1
=
(23)
R1
V
V2R
R2
REF
DIV
=
(24)
R2
R1
V
V3R
R3
REF
DIV
=
(25)
R3R2R1
V
V4R
R
REF
DIV
=4
(26)
R5 = R
DIV
R1 R2 R3 R4 (27)
To create a mirrored voltage sequence, add a resistor, R
MIRROR
,
between the pull-up resistor (R
PULLUP
) and the load capacitor
(C
L
) as shown in Figure 27.
Figure 27. Circuit Configuration for a Mirrored Voltage Sequencer
Figure 27 shows the circuit configuration for a mirrored voltage
sequencer. When SEQ changes from low to high impedance, the
response is similar to Figure 26. When SEQ changes from high
impedance to low, the load capacitor (C
L
) starts to discharge at a
rate set by R
MIRROR
. The delay of each comparator is dependent
on the threshold voltage previously set for t
1
to t
4
. The result is a
mirrored power-down sequence.
SEQ
V
C
L
OUT4
OUT3
OUT2
OUT1
V1
V2
V3
V4
t
4
t
3
t
2
t
1
12206-126
OUT4
OUT3
OUT2
OUT1
R2
V2
R3
V3
R4
V4
R5
R1
V1
R
PULLUP
R
MIRROR
V
REF
/V
CC
C
L
SEQ
12206-127
U1
U2
U3
U4
Rev. 0 | Page 12 of 15
Data Sheet ADCMP391
Figure 28. Mirrored Voltage Sequencer Timing Diagram
The timing diagram for the mirrored voltage sequencer is
shown in Figure 28.
Equation 18 through Equation 21 must account for the
additional resistance, R
MIRROR
, in the calculations of the voltage
thresholds. To calculate these new thresholds, see Equation 28
through Equation 31.
( )
=
+
L
MIRROR
PULLUP
1
CRR
t
REF
eVV1 1
(28)
( )
=
+
L
MIRROR
PULLUP
2
CRR
t
REF
eVV2 1
(29)
( )
=
+
L
MIRROR
PULLUP
3
CR
R
t
REF
e
V
V3
1
(30)
( )
=
+
L
MIRROR
PULLUP
4
CRR
t
REF
eVV4 1
(31)
R
MIRROR
provides the mirrored delay by prolonging the discharge
time of the capacitor. The mirrored voltage sequencer uses the
same threshold in Equation 28 to Equation 31 in a decreasing
order. To calculate the exact value of the mirrored delay time,
see Equation 32 through Equation 35.
=
REF
L
MIRROR
5
V
V
CRt
4
ln
(32)
=
REF
L
MIRROR
6
V
V
CRt
3
ln
(33)
=
REF
L
MIRROR
7
V
V
CRt
2
ln
(34)
=
REF
L
MIRROR
8
V
V1
CRt ln
(35)
MIRRORED VOLTAGE SEQUENCER EXAMPLE
To illustrate how the mirrored voltage sequencer works, see
Figure 25 and then consider a system that uses a V
REF
of 1 V and
requires a delay of 50 ms when SEQ changes from low to high
impedance, and between each regulator when turning on. These
considerations require a rise time of at least 200 ms for the pull-up
resistor (R
PULLUP
) and the load capacitor (C
L
). The sum of the
resistance of R
MIRROR
and R
PULLUP
must be large enough to charge the
capacitor longer than the minimum required delay. For a
symmetrical mirrored power-down sequence, the value of R
MIRROR
must be much larger than R
PULLUP
. A 10 kΩ R
PULLUP
value limits the
pull-down current to 100 µA while giving a reasonable value for
R
MIRROR
. A typical 1 µF capacitor together with a 150 kΩ R
MIRROR
value gives a value of
t
MAX
= 2.197((160 × 10
3
) × (1 × 10
−6
)) = 351 ms (36)
The threshold voltage required by each comparator is set by
Equation 28 to Equation 31. For example,
=
×××
×
6
101
3
10160
3
1050
1 eVV1
REF
where V1 = 268.38 mV.
Therefore, V2 = 464.74 mV, V3 = 608.39 mV, and V4 =
713.5 mV.
Next, consider 10 µA as the maximum current (I
DIV
) flowing
through the resistor divider network. This current gives the total
resistance of the divider network (R
DIV
) and the individual
resistor values using Equation 22 to Equation 27, resulting in
the following:
R
DIV
= 100 kΩ
R1 = 26.84 kΩ ≈ 26.7 kΩ
R2 = 19.64 kΩ ≈ 19.6 kΩ
R3 = 14.37 kΩ ≈ 14.3 kΩ
R4 = 10.51 kΩ ≈ 10.5 kΩ
R5 = 28.65 kΩ ≈ 28.7 kΩ
SEQ
V
C
L
OUT4
OUT3
OUT2
OUT1
t
4
t
3
t
2
t
7
t
8
t
1
t
5
t
6
V1
V2
V3
V4
V4
V3
V2
V1
12206-200
Rev. 0 | Page 13 of 15
ADCMP391 Data Sheet
Resistor values from the calculation are nonindustry standard,
using industry standard resistor values resulted in a new R
DIV
value of 99.8 kΩ. Due to the discrepancy of the calculated resistor
value to the industry standard value, the threshold of each
comparator also changed. Calculate the new threshold values
by using a simple voltage divider formula:
V1 = V
REF
R1/R
DIV
(37)
where V1 =
( )
99.8
26.7V1
= 267.54 mV.
Therefore, V2 = 463.93 mV, V3 = 607.21 mV, and V4 = 712.42 mV.
Because the threshold of each comparator has changed, the time
when each comparator changes its output has also changed.
Calculate the new delay values for each comparator by using the
following equation:
( )
+=
REF
MIRROR
PULLUPL
1
V
V1
RRC
t 1ln
(38)
where t
1
= −1 µF(10 kΩ + 150 kΩ)ln
1
mV54
.267
1
= 49.81 ms.
Therefore, t
2
= 99.78 ms, t
3
= 149.52 ms, and t
4
= 199.4 ms.
To calculate t
5
through t
8
, use Equation 32 to Equation 35:
=
REF
L
MIRROR
5
V
V4
lnCRt
where t
5
= −150 kΩ × 1 µF × ln
1
mV712.42
= 50.86 ms.
Therefore, t
6
= 74.83 ms, t
7
= 115.2 ms, and t
8
= 197.78 ms.
THRESHOLD AND TIMEOUT PROGRAMMABLE
VOLTAGE SUPERVISOR
Figure 29 shows a circuit configuration for a programmable
threshold and timeout circuit. The timeout, t
RESET
, defines the
duration that the input voltage (V
IN
) must be kept above the
threshold voltage to toggle the
RESET
signal, preventing the
device from operating when V
IN
is not stable. If V
IN
falls below
the threshold voltage, the
RESET
signal toggles quickly.
Figure 29. Programmable Threshold and Timeout Circuit
Figure 30. Threshold and Timeout Programmable Voltage Supervisor
Timing Diagram
During startup, the ADCMP391 guarantees a low output state
when V
CC
is still below the UVLO threshold, preventing the
voltage supervisor from toggling.
When V
IN
reaches the threshold set by the resistor divider (R1
and R2) and V
REF
, OUT1 changes from low to high and starts to
charge the timeout capacitor (C
T
). If V
IN
is kept above the threshold
voltage and the voltage in C
T
reaches V
REF
, OUT2 toggles. If V
IN
falls below the threshold voltage while C
T
is charging, the timeout
capacitor quickly discharges, preventing OUT2 from toggling
while V
IN
is not stable.
In the condition that V
IN
is tied to V
CC
, the circuit operates
when V
CC
is more than the minimum operating voltage.
The threshold voltage (V
TH
) is configured by changing the
resistor divider or V
REF
. Calculate the threshold voltage by
+=
R2
R1
VV
REF
TH
1
(39)
Timeout is adjusted by changing the values of the pull-up
resistor or the timeout capacitor. To set the timeout value,
determine the allowable current flowing through R
PULLUP
and
I
PULLUP
. When I
PULLUP
is known, calculate R
PULLUP
and C
T
by the
following formulas:
R
PULLUP
= V
CC
/I
PULLUP
(40)
=
CC
REF
PULLUP
RESET
T
V
V
R
t
C
1ln
(41)
RESET
OUT2
OUT1
U2
U1
R
PULLU
P
R1
R2
V
CC
C
T
V
IN
V
REF
12206-129
RESET
V
TH
V
IN
t
RESET
t
RESET
12206-130
Rev. 0 | Page 14 of 15

ADCMP391ARZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Comparators Single Comparator Rail-Rail, Low Power
Lifecycle:
New from this manufacturer.
Delivery:
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