MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
16 ______________________________________________________________________________________
progress. In software power-down mode, the serial
interface remains active, waiting for a new control byte
to start conversion and switch to full-power mode.
Once the conversion is completed, the device goes
into the programmed power mode until a new control
byte is written.
The power-up delay is dependent on the power-down
state. Software low-power modes will be able to start
conversion immediately when running at decreased
clock rates (see Power-Down Sequencing). During
power-on reset, when exiting software full power-down
mode or exiting hardware shutdown, the device goes
immediately into full-power mode and is ready to con-
vert after 2µs when using an external reference. When
using the internal reference, wait for the typical power-
up delay from a full power-down (software or hard-
ware), as shown in Figure 9.
Software Power-Down
Software power-down is activated using bits PD1 and
PD0 of the control byte. When software shutdown is
asserted, the ADC completes the conversion in
progress and powers down into the specified low-
quiescent-current state (2µA, 0.9mA, or 1.3mA).
The first logic 1 on DIN is interpreted as a start bit and
puts the MAX1280/MAX1281 into their full-power mode.
Following the start bit, the data input word or control
byte also determines the next power-down state. For
example, if the DIN word contains PD1 = 0 and PD0 =
1, a 0.9mA power-down starts after the conversion.
112
B11 B6 B0 B11 B6 B0 B11 B6
168 1 12 1685 1 12 16851
SETCS CONTROL BYTE 2S CONTROL BYTE 1SDIN
SCLK
DOUT
SSTRB
CS
CONTROL BYTE 0
CONVERSION RESULT 0 CONVERSION RESULT 1
5
HIGH-Z
HIGH-Z
Figure 8. Continuous 16-Clock/Conversion Timing
PD1/PD0 MODE
CONVERTING
AFTER
CONVERSION
INPUT COMPARATOR REFERENCE
00
Full Power-Down
(FULLPD)
2.5mA 2µA Off Off
01
Fast Power-Down
(FASTPD)
2.5mA 0.9mA Reduced Power On
10
Reduced-Power
Mode (REDPD)
2.5mA 1.3mA Reduced Power On
11 Operating Mode 2.5mA 2.0mA Full Power On
CIRCUIT SECTIONS*TOTAL SUPPLY CURRENT
Table 4. Software-Controlled Power Modes
*Circuit operation between conversions; during conversion, all circuits are fully powered up.
MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
______________________________________________________________________________________ 17
Table 4 details the four power modes with the corre-
sponding supply current and operating sections. For
data rates achievable in software power-down modes,
see Power-Down Sequencing section.
Hardware Power-Down
Pulling SHDN low places the converter in hardware
power-down. Unlike software power-down mode, the
conversion is terminated immediately. When returning
to normal operation from SHDN with an external refer-
ence, the MAX1280/MAX1281 can be considered fully
powered-up within 2µs of actively pulling SHDN high.
When using the internal reference, the conversion
should be initiated only after the reference has settled;
its recovery time depends on the external bypass
capacitors and shutdown duration.
Power-Down Sequencing
The MAX1280/MAX1281’s automatic power-down
modes can save considerable power when operating at
less than maximum sample rates. Figures 10 and 11
show the average supply current as a function of the
sampling rate.
Using Full Power-Down Mode
Full power-down mode (FULLPD) achieves the lowest
power consumption at up to 1000 conversions per
channel per second. Figure 10a shows the MAX1281’s
power consumption for 1- or 8-channel conversions
using full power-down mode (PD1 = PD0 = 0), with the
internal reference and the maximum clock speed. A
0.01µF bypass capacitor plus the internal 17k refer-
ence resistor at REFADJ forms an RC filter with a 200µs
time constant. To achieve full 12-bit accuracy, 10 time
constants or 2ms are required after power-up if the
bypass capacitor is fully discharged between conver-
sions. Waiting this 2ms in FASTPD mode or reduced-
power mode (REDP) instead of full power-down mode
can further reduce power consumption. This is
achieved by using the sequence shown in Figure 12a.
Figure 10b shows the MAX1281’s power consumption
for 1- or 8-channel conversions using FULLPD mode
(PD1 = PD0 = 0), an external reference, and the maxi-
mum clock speed. One dummy conversion to power-up
the device is needed, but no wait-time is necessary to
start the second conversion, thereby achieving lower
power consumption at up to the full sampling rate.
Using Fast Power-Down and
Reduced-Power Modes
FASTPD and REDP modes achieve the lowest power
consumption at speeds close to the maximum sample
rate. Figure 11 shows the MAX1281’s power consump-
tion in FASTPD mode (PD1 = 0, PD0 = 1), REDP mode
(PD1 = 1, PD0 = 0), and (for comparison) normal
operating mode (PD1 = 1, PD0 = 1). The figure shows
0
0.50
0.25
1.00
0.75
1.25
1.50
0.0001 0.010.001 0.1 1 10
TIME IN SHUTDOWN (s)
REFERENCE POWER-UP DELAY (ms)
MAX1281
V
DD1
=
V
DD2
=
3.0V
C
LOAD
= 20pF
CODE = 101010000000
1000
100
10
1
0.1 101 100 1k 10k
SAMPLING RATE (sps)
SUPPLY CURRENT (µA)
8 CHANNELS
1 CHANNEL
10,000
1000
10
100
1
1 10010 1k 10k 100k
SAMPLING RATE (sps)
SUPPLY CURRENT (µA)
MAX1281
V
DD1
=
V
DD2
=
3.0V
C
LOAD
= 20pF
CODE = 101010000000
8 CHANNELS
1 CHANNEL
Figure 9. Reference Power-Up Delay vs. Time in Shutdown
Figure 10a. Average Supply Current vs. Sample Rate (Using
FULLPD and Internal Reference)
Figure 10b. Average Supply Current vs. Sampling Rate (Using
FULLPD and External Reference)
MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
18 ______________________________________________________________________________________
power consumption using the specified power-down
mode, with the internal reference and the maximum
clock speed. The clock speed in FASTPD or REDP
should be limited to 4.8MHz for the MAX1280/
MAX1281. FULLPD mode may provide increased power
savings in applications where the MAX1280/
MAX1281 are inactive for long periods of time, but
where intermittent bursts of high-speed conversions are
required.
Internal and External References
The MAX1280/MAX1281 can be used with an internal
or external reference. An external reference can be
connected directly at REF or at the REFADJ pin.
An internal buffer is designed to provide 2.5V at REF for
both the MAX1280/MAX1281. The internally trimmed
1.22V reference is buffered with a gain of +2.05V/V.
Internal Reference
The MAX1280/MAX1281’s full-scale range with the inter-
nal reference is 2.5V for unipolar inputs and ±1.25V for
bipolar inputs. The internal reference voltage is
adjustable to ±100mV with the circuit of Figure 13.
External Reference
An external reference can be placed at either the input
(REFADJ) or the output (REF) of the internal reference-
buffer amplifier. The REFADJ input impedance is typical-
ly 17k. At REF, the DC input resistance is a minimum of
2.5
2.0
1.0
1.5
0.5
0
150
250
100
50
200
300 350
SAMPLING RATE (sps)
SUPPLY CURRENT (mA)
MAX1281, V
DD1
=
V
DD2
=
3.0V
C
LOAD
= 20pF
CODE = 101010000000
REDP
FASTPD
NORMAL OPERATION
Figure 11. Average Supply Current vs. Sampling Rate (Using
REPD, FASTPD, and Normal Operation and Internal Reference)
Figure 12a. Full Power-Down Timing
RE FADJ
1.22V
1.22V
0V
2.5mA
2.5mA
1.3mA OR 0.9mA
DIN
I
VDD1
+ I
VDD2
REF
FULLPD
REDP
WAIT 2ms (10 x RC)
FULLPD
1
0
0
11
γ
= RC = 17k
x 0.01
µ
F
DUMMY CONVERSION
1
1
0
0
0
2.5V
2.5mA
0mA
0mA
2.5V
0V
Figure 12b. Reduced-Power/Fast Power-Down Timing
2.5V (ALWAYS ON)
2.5mA
2.5mA
DIN
I
VDD1
+ I
VDD2
REF
REDPD
REDP FASTPD
1
1
0
11
1
0
0
1
2.5mA
1.3mA
1.3mA
0.9mA

MAX1281BCUP+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 12-Bit 8Ch 300ksps 3.6V Precision ADC
Lifecycle:
New from this manufacturer.
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