MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
______________________________________________________________________________________ 19
18k. During conversion, an external reference at REF
must deliver up to 350µA DC load current and have 10
or less output impedance. If the reference has a higher
output impedance or is noisy, bypass it close to the REF
pin with a 4.7µF capacitor.
Using the REFADJ input makes buffering the external
reference unnecessary. To use the direct REF input,
disable the internal buffer by connecting REFADJ to
V
DD1
.
Transfer Function
Table 5 shows the full-scale voltage ranges for unipolar
and bipolar modes. Figure 14 depicts the nominal,
unipolar input/output (I/O) transfer function, and Figure
15 shows the bipolar I/O transfer function. Code transi-
tions occur halfway between successive-integer LSB
values. Output coding is binary, with 1LSB = 610µV
for unipolar and bipolar operation.
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards; wire-
wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
Figure 16 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at GND. Connect all analog grounds
to the star ground. Connect the digital system ground
to star ground at this point only. For lowest-noise opera-
tion, the ground return to the star ground’s power sup-
ply should be low impedance and as short as possible.
High-frequency noise in the V
DD1
power supply may
affect the high-speed comparator in the ADC. Bypass
the supply to the star ground with 0.1µF and 10µF
capacitors, located close to pin 20 of the MAX1280/
MAX1281. Minimize capacitor lead lengths for best
supply-noise rejection. If the power supply is very
noisy, a 10 resistor can be connected as a lowpass
filter (Figure 16).
+3.3V
510k
24k
100k
0.01µF
12
REFADJ
MAX1281
Figure 13. MAX1281 Reference-Adjust Circuit
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
11 . . . 101
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
123
0
(COM)
FS
FS - 3/2LSB
FS = V
REF
+ V
COM
ZS = V
COM
INPUT VOLTAGE (LSB)
1 LSB =
V
REF
4096
Figure 14. Unipolar Transfer Function, Full Scale (FS) = V
REF
+ V
COM
, Zero Scale (ZS) = V
COM
011 . . . 111
011 . . . 110
000 . . . 010
000 . . . 001
000 . . . 000
111 . . . 111
111 . . . 110
111 . . . 101
100 . . . 001
100 . . . 000
- FS
COM*
INPUT VOLTAGE (LSB)
OUTPUT CODE
ZS = COM
+FS - 1LSB
*V
COM
V
REF
/ 2
+ V
COM
FS
=
V
REF
2
-FS = + V
COM
-V
REF
2
1 LSB =
V
REF
4096
Figure 15. Bipolar Transfer Function, Full Scale (FS) =
V
REF
/ 2 + V
COM
, Zero Scale (ZS) = V
COM
MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
20 ______________________________________________________________________________________
High-Speed Digital Interfacing with QSPI
The MAX1280/MAX1281 can interface with QSPI using
the circuit in Figure 17 (f
SCLK
= 4.0MHz, CPOL = 0,
CPHA = 0). This QSPI circuit can be programmed to do
a conversion on each of the eight channels. The result
is stored in memory without taxing the CPU, since QSPI
incorporates its own microsequencer.
TMS320LC3x Interface
Figure 18 shows an application circuit that interfaces
the MAX1280/MAX1281 to the TMS320 in external clock
mode. The timing diagram for this interface circuit is
shown in Figure 19.
Use the following steps to initiate a conversion in the
MAX1280/MAX1281 and to read the results:
1) The TMS320 should be configured with CLKX (trans-
mit clock) as an active-high output clock and with
CLKR (TMS320 receive clock) as an active-high
input clock. CLKX and CLKR on the TMS320 are
connected with the MAX1280/MAX1281’s SCLK
input.
2) The MAX1280/MAX1281’s CS pin is driven low by
the TMS320’s XF_ I/O port to enable data to be
clocked into the MAX1280/MAX1281’s DIN pin.
3) An 8-bit word (1XXXXX11) should be written to the
MAX1280/MAX1281 to initiate a conversion and
place the device into normal operating mode. See
Table 1 to select the proper XXXXX bit values for
your specific application.
4) The MAX1280/MAX1281’s SSTRB output is moni-
tored through the TMS320’s FSR input. A falling
edge on the SSTRB output indicates that the conver-
sion is in progress and data is ready to be received
from the MAX1280/MAX1281.
5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits repre-
sent the 12-bit conversion result followed by four
trailing bits, which should be ignored.
6) Pull CS high to disable the MAX1280/MAX1281 until
the next conversion is initiated.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1280/MAX1281
are measured using the endpoint method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (t
AJ
) is the sample-to-sample variation in
the time between the samples.
V
DD1
V
DD2
GND
SUPPLIES
DGNDV
DD
V
DD2
COM
GNDV
DD1
DIGITAL
CIRCUITRY
R* = 10
*OPTIONAL
MAX1280
MAX1281
Figure 16. Power-Supply Grounding Connection
UNIPOLAR MODE BIPOLAR MODE
Full Scale Zero Scale
Positive Zero Negative
Full Scale Scale Full Scale
V
REF
+ V
COM
COM
V
REF
/ 2
V
COM
-V
REF
/ 2
+ V
COM
+ V
COM
Table 5. Full Scale and Zero Scale
MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
______________________________________________________________________________________ 21
Aperture Delay
Aperture delay (t
AD
) is the time defined between the
falling edge of the sampling clock and the instant when
an actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, Signal-to-noise ratio (SNR) is the ratio of full-
scale analog input (RMS value) to the RMS quantization
error (residual error). The ideal theoretical minimum
analog-to-digital noise is caused by quantization error
only and results directly from the ADC’s resolution (N
bits):
SNR = (6.02
N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is calculated by taking
the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamen-
tal, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise ratio plus distortion (SINAD) is the ratio
of the fundamental input frequency’s RMS amplitude to
RMS equivalent of all other ADC output signals.
SINAD (dB) = 20
log (Signal
RMS
/ Noise
RMS
)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
MAX1280
MAX1281
MC683XX
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
SHDN
V
DD2
V
DD1
SCLK
CS
DIN
SSTRB
DOUT
GND
REFADJ
REF
V
DD1
(POWER SUPPLIES)
SCK
PCS0
MOSI
MISO
0.1µF
10µF
(GND)
4.7µF
0.01µF
ANALOG
INPUTS
+3V OR +5V
+3V OR +5V
Figure 17. QSPI Connections
XF
CLKX
CLKR
DX
DR
FSR
CS
SCLK
DIN
DOUT
SSTRB
TMS320LC3x
MAX1280
MAX1281
Figure 18. MAX1280/MAX1281-to-TMS320 Serial Interface

MAX1281BCUP+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 12-Bit 8Ch 300ksps 3.6V Precision ADC
Lifecycle:
New from this manufacturer.
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