SJA1000/N1,112 Datasheet SJA1000T/N1,118, SJA1000T/N1,112, SJA1000/N1,112 | P13-P15

2000 Jan 04 13

Philips Semiconductors Product speciﬁcation

Stand-alone CAN controller SJA1000

Notes

1. Any write access to the control register has to set this bit to logic 0 (reset value is logic 0).

2. In the PCA82C200 this bit was used to select the synchronization mode. Because this mode is not longer

implemented, setting this bit has no influence on the microcontroller. Due to software compatibility setting this bit is

allowed. This bit will not change after hardware or software reset. In addition the value written by users software is

reflected.

3. Reading this bit will always reflect a logic 1.

4. During a hardware reset or when the bus status bit is set to logic 1 (bus-off), the reset request bit is set to logic 1

(present). If this bit is accessed by software, a value change will become visible and takes effect first with the next

positive edge of the internal clock which operates with

⁄

of the external oscillator frequency. During an external reset

the microcontroller cannot set the reset request bit to logic 0 (absent). Therefore, after having set the reset request

bit to logic 0, the microcontroller must check this bit to ensure that the external reset pin is not being held LOW.

Changes of the reset request bit are synchronized with the internal divided clock. Reading the reset request bit

reflects the synchronized status.

After the reset request bit is set to logic 0 the SJA1000 will wait for:

a) One occurrence of bus-free signal (11 recessive bits), if the preceding reset request has been caused by a

hardware reset or a CPU-initiated reset

b) 128 occurrences of bus-free, if the preceding reset request has been caused by a CAN controller initiated bus-off,

before re-entering the bus-on mode; it should be noted that several registers are modified if the reset request bit

was set (see also Table 2).

6.3.4 COMMAND REGISTER (CMR)

A command bit initiates an action within the transfer layer of the SJA1000. The command register appears to the

microcontroller as a write only memory. If a read access is performed to this address the byte ‘11111111’ is returned.

Between two commands at least one internal clock cycle is needed to process. The internal clock is divided by two from

the external oscillator frequency.

CR.1 RIE Receive Interrupt Enable 1 enabled; when a message has been received

without errors, the SJA1000 transmits a receive

interrupt signal to the microcontroller

0 disabled; the microcontroller receives no transmit

interrupt signal from the SJA1000

CR.0 RR Reset Request; note 4 1 present; detection of a reset request results in

aborting the current transmission/reception of a

message and entering the reset mode

0 absent; on the ‘1-to-0’ transition of the reset

request bit, the SJA1000 returns to the operating

mode

BIT SYMBOL NAME VALUE FUNCTION

2000 Jan 04 14

Philips Semiconductors Product speciﬁcation

Stand-alone CAN controller SJA1000

Table 4 Bit interpretation of the command register (CMR); CAN address 1

Notes

1. The SJA1000 will enter sleep mode if the sleep bit is set to logic 1 (sleep); there is no bus activity and no interrupt is

pending. Setting of GTS with at least one of the previously mentioned exceptions valid will result in a wake-up

interrupt. After sleep mode is set, the CLKOUT signal continues until at least 15 bit times have passed, to allow a

host microcontroller clocked via this signal to enter its own standby mode before the CLKOUT goes LOW.

The SJA1000 will wake up when one of the three previously mentioned conditions is negated: after ‘Go To Sleep’ is

set LOW (wake-up), there is bus activity or

INT is driven LOW (active). On wake-up, the oscillator is started and a

wake-up interrupt is generated. A sleeping SJA1000 which wakes up due to bus activity will not be able to receive

this message until it detects 11 consecutive recessive bits (bus-free sequence). It should be noted that setting of GTS

is not possible in reset mode. After clearing of reset request, setting of GTS is possible first, when bus-free is detected

again.

2. This command bit is used to clear the data overrun condition indicated by the data overrun status bit. As long as the

data overrun status bit is set no further data overrun interrupt is generated. It is allowed to give the clear data overrun

command at the same time as a release receive buffer command.

3. After reading the contents of the receive buffer, the microcontroller can release this memory space of the RXFIFO

by setting the release receive buffer bit to logic 1. This may result in another message becoming immediately

available within the receive buffer. This event will force another receive interrupt, if enabled. If there is no other

message available no further receive interrupt is generated and the receive buffer status bit is cleared.

4. The abort transmission bit is used when the CPU requires the suspension of the previously requested transmission,

e.g. to transmit a more urgent message before. A transmission already in progress is not stopped. In order to see if

the original message had been either transmitted successfully or aborted, the transmission complete status bit

should be checked. This should be done after the transmit buffer status bit has been set to logic 1 (released) or a

transmit interrupt has been generated.

5. If the transmission request was set to logic 1 in a previous command, it cannot be cancelled by setting the

transmission request bit to logic 0. The requested transmission may be cancelled by setting the abort transmission

bit to logic 1.

BIT SYMBOL NAME VALUE FUNCTION

CMR.7 −− −reserved

CMR.6 −− −reserved

CMR.5 −− −reserved

CMR.4 GTS Go To Sleep; note 1 1 sleep; the SJA1000 enters sleep mode if no CAN

interrupt is pending and there is no bus activity

0 wake up; SJA1000 operates normal

CMR.3 CDO Clear Data Overrun;

note 2

1 clear; data overrun status bit is cleared

0 no action

CMR.2 RRB Release Receive Buffer;

note 3

1 released; the receive buffer, representing the

message memory space in the RXFIFO is

released

0 no action

CMR.1 AT Abort Transmission;

note 4

1 present; if not already in progress, a pending

transmission request is cancelled

0 absent; no action

CMR.0 TR Transmission Request;

note 5

1 present; a message will be transmitted

0 absent; no action

2000 Jan 04 15

Philips Semiconductors Product speciﬁcation

Stand-alone CAN controller SJA1000

6.3.5 STATUS REGISTER (SR)

The content of the status register reflects the status of the SJA1000. The status register appears to the microcontroller

as a read only memory.

Table 5 Bit interpretation of the status register (SR); CAN address 2

BIT SYMBOL NAME VALUE FUNCTION

SR.7 BS Bus Status; note 1 1 bus-off; the SJA1000 is not involved in bus

activities

0 bus-on; the SJA1000 is involved in bus activities

SR.6 ES Error Status; note 2 1 error; at least one of the error counters has

reached or exceeded the CPU warning limit

0 ok; both error counters are below the warning limit

SR.5 TS Transmit Status; note 3 1 transmit; the SJA1000 is transmitting a message

0 idle; no transmit message is in progress

SR.4 RS Receive Status; note 3 1 receive; the SJA1000 is receiving a message

0 idle; no receive message is in progress

SR.3 TCS Transmission Complete

Status; note 4

1 complete; the last requested transmission has

been successfully completed

0 incomplete; the previously requested transmission

is not yet completed

SR.2 TBS Transmit Buffer Status;

note 5

1 released; the CPU may write a message into the

transmit buffer

0 locked; the CPU cannot access the transmit

buffer; a message is waiting for transmission or is

already in process

SR.1 DOS Data Overrun Status;

note 6

1 overrun; a message was lost because there was

not enough space for that message in the RXFIFO

0 absent; no data overrun has occurred since the

last clear data overrun command was given

SR.0 RBS Receive Buffer Status;

note 7

1 full; one or more messages are available in the

RXFIFO

0 empty; no message is available

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SJA1000/N1,112

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IC STAND-ALONE CAN CTRLR 28-DIP

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SJA1000/N1,112

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