SJA1000/N1,112 Datasheet SJA1000T/N1,118, SJA1000T/N1,112, SJA1000/N1,112 | P25-P27

2000 Jan 04 25

Philips Semiconductors Product speciﬁcation

Stand-alone CAN controller SJA1000

Output control OCR.7 OCTP1 Output Control

Transistor P1

OCR.6 OCTN1 Output Control

Transistor N1

OCR.5 OCPOL1 Output Control Polarity 1 X X

OCR.4 OCTP0 Output Control

Transistor P0

OCR.3 OCTN0 Output Control

Transistor N0

OCR.2 OCPOL0 Output Control Polarity 0 X X

OCR.1 OCMODE1 Output Control Mode 1 X X

OCR.0 OCMODE0 Output Control Mode 0 X X

Arbitration lost

capture

− ALC Arbitration Lost Capture 0 X

Error code

capture

− ECC Error Code Capture 0 X

Error warning

limit

− EWLR Error Warning Limit

96 X

RX error

counter

− RXERR Receive Error Counter 0 (reset) X; note 4

TX error

counter

− TXERR Transmit Error Counter 0 (reset) X; note 4

TX buffer − TXB Transmit Buffer X X

RX buffer − RXB Receive Buffer X; note 5 X; note 5

ACR 0 to 3 − ACR0 to ACR3 Acceptance Code

Registers

AMR 0 to 3 − AMR0 to AMR3 Acceptance Mask

Registers

RX message

counter

− RMC RX Message Counter 0 0

RX buffer start

address

− RBSA RX Buffer Start Address 00000000 X

Clock divider − CDR Clock Divider Register 00000000 Intel;

00000101

Motorola

VALUE

RESET BY

HARDWARE

SETTING MOD.0

BY SOFTWARE

OR DUE TO

BUS-OFF

2000 Jan 04 26

Philips Semiconductors Product speciﬁcation

Stand-alone CAN controller SJA1000

Notes

1. X means that the value of these registers or bits is not influenced.

2. Remarks in brackets explain functional meaning.

3. On bus-off the error warning interrupt is set, if enabled.

4. If the reset mode was entered due to a bus-off condition, the receive error counter is cleared and the transmit error

counter is initialized to 127 to count-down the CAN-defined bus-off recovery time consisting of 128 occurrences of

11 consecutive recessive bits.

5. Internal read/write pointers of the RXFIFO are reset to their initial values. A subsequent read access to the RXB

would show undefined data values (parts of old messages).

If a message is transmitted, this message is written in parallel to the receive buffer. A receive interrupt is generated

only if this transmission was forced by the self reception request. So, even if the receive buffer is empty, the last

transmitted message may be read from the receive buffer until it is overwritten by the next received or transmitted

message.

Upon a hardware reset, the RXFIFO pointers are reset to the physical RAM address ‘0’. Setting CR.0 by software or

due to the bus-off event will reset the RXFIFO pointers to the currently valid FIFO start address (RBSA register)

which is different from the RAM address ‘0’ after the first release receive buffer command.

6.4.3 MODE REGISTER (MOD)

The contents of the mode register are used to change the behaviour of the CAN controller. Bits may be set or reset by

the CPU which uses the control register as a read/write memory. Reserved bits are read as logic 0.

Table 12 Bit interpretation of the mode register (MOD); CAN address ‘0’

BIT SYMBOL NAME VALUE FUNCTION

MOD.7 −− −reserved

MOD.6 −− −reserved

MOD.5 −− −reserved

MOD.4 SM Sleep Mode; note 1 1 sleep; the CAN controller enters sleep mode if no

CAN interrupt is pending and if there is no bus

activity

0 wake-up; the CAN controller wakes up if sleeping

MOD.3 AFM Acceptance Filter Mode;

note 2

1 single; the single acceptance ﬁlter option is

enabled (one ﬁlter with the length of 32 bit is

active)

0 dual; the dual acceptance ﬁlter option is enabled

(two ﬁlters, each with the length of 16 bit are

active)

MOD.2 STM Self Test Mode; note 2 1 self test; in this mode a full node test is possible

without any other active node on the bus using the

self reception request command; the

CAN controller will perform a successful

transmission, even if there is no acknowledge

received

0 normal; an acknowledge is required for successful

transmission

2000 Jan 04 27

Philips Semiconductors Product speciﬁcation

Stand-alone CAN controller SJA1000

Notes

1. The SJA1000 will enter sleep mode if the sleep mode bit is set to logic 1 (sleep); then there is no bus activity and no

interrupt is pending. Setting of SM with at least one of the previously mentioned exceptions valid will result in a

wake-up interrupt. After sleep mode is set, the CLKOUT signal continues until at least 15 bit times have passed, to

allow a host microcontroller clocked via this signal to enter its own standby mode before the CLKOUT goes LOW.

The SJA1000 will wake up when one of the three previously mentioned conditions is negated: after SM is set LOW

(wake-up), there is bus activity or INT is driven LOW (active). On wake-up, the oscillator is started and a wake-up

interrupt is generated. A sleeping SJA1000 which wakes up due to bus activity will not be able to receive this

message until it detects 11 consecutive recessive bits (bus-free sequence). It should be noted that setting of SM is

not possible in reset mode. After clearing of reset mode, setting of SM is possible first, when bus-free is detected

again.

2. A write access to the bits MOD.1 to MOD.3 is only possible, if the reset mode is entered previously.

3. This mode of operation forces the CAN controller to be error passive. Message transmission is not possible.

The listen only mode can be used e.g. for software driven bit rate detection and ‘hot plugging’. All other functions can

be used like in normal mode.

4. During a hardware reset or when the bus status bit is set to logic 1 (bus-off), the reset mode bit is also set to logic 1

(present). If this bit is accessed by software, a value change will become visible and takes effect first with the next

positive edge of the internal clock which operates at half of the external oscillator frequency. During an external reset

the microcontroller cannot set the reset mode bit to logic 0 (absent). Therefore, after having set the reset mode bit to

logic 1, the microcontroller must check this bit to ensure that the external reset pin is not being held HIGH. Changes

of the reset request bit are synchronized with the internal divided clock. Reading the reset request bit reflects the

synchronized status. After the reset mode bit is set to logic 0 the CAN controller will wait for:

a) One occurrence of bus-free signal (11 recessive bits), if the preceding reset has been caused by a hardware reset

or a CPU-initiated reset.

b) 128 occurrences of bus-free, if the preceding reset has been caused by a CAN controller initiated bus-off, before

re-entering the bus-on mode.

MOD.1 LOM Listen Only Mode;

notes 2 and 3

1 listen only; in this mode the CAN controller would

give no acknowledge to the CAN-bus, even if a

message is received successfully; the error

counters are stopped at the current value

0 normal

MOD.0 RM Reset Mode; note 4 1 reset; detection of a set reset mode bit results in

aborting the current transmission/reception of a

message and entering the reset mode

0 normal; on the ‘1-to-0’ transition of the reset mode

bit, the CAN controller returns to the operating

mode

BIT SYMBOL NAME VALUE FUNCTION

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57 P58-P60 P61-P63 P64-P66 P67-P68

SJA1000/N1,112

Mfr. #:

Buy SJA1000/N1,112

Manufacturer:

NXP Semiconductors

Description:

IC STAND-ALONE CAN CTRLR 28-DIP

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

SJA1000/N1,112

SJA1000/N1,112

Products related to this Datasheet