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5V49EE902NLGI8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
IDT5V49EE902
EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR 19
IDT5V49EE902 REV Q 071015
DC Electrical Characteristics for LVDS
Power Supply Characteristics for LVDS Outputs
1
Note 1: Output banks 4 and 5 are toggling. Other output banks are powered down.
Note 2: The termination resistors are excluded from these measurements.
DC Electrical Characteristics for LVPECL
Symbol Parameter Min Typ Max Unit
V
OT
(+) Differential Output Voltage for the TRUE binary state 247 454 mV
V
OT
(-) Differential Output Voltage for the FALSE binary state -247 -454 mV
V
OT
Change in V
OT
between Complimentary Output States 50 mV
V
OS
Output Common Mode Voltage (Offset Voltage) 1.125 1.2 1.375 V
V
OS
Change in V
OS
between Complimentary Output States 50 mV
I
OS
Outputs Short Circuit Current, V
OUT
+ or V
OUT
- = 0V or V
DD
924mA
I
OSD
Differential Outputs Short Circuit Current, V
OUT
+ = V
OUT
-612mA
Symbol Parameter Test Conditions
2
Typ Max Unit
I
DDQ
Quiescent V
DD
Power
Supply Current
REF = LOW
Outputs enabled, all outputs unloaded
68 90 mA
I
DDD
Dynamic V
DD
Power Supply
Current per Output
V
DD
= Max., C
L
= 0pF 30 45 µA/MHz
I
TOT
Total Powe r V
DD
Supply
Current
F
REFERENCE CLOCK
= 100 MHz, C
L
= 2 pF 86 130 mA
F
REFERENCE CLOCK
= 200 MHz, C
L
= 2 pF 100 150
F
REFERENCE CLOCK
= 400 MHz, C
L
= 2 pF 122 190
Symbol Parameter Min Typ Max Unit
V
OH
Output Voltage HIGH, terminated through 50 tied to V
DD
-2 V V
DD
-1.2 V
DD
-0.9 V
V
OL
Output Voltage LOW, terminated through 50 tied to V
DD
-2 V V
DD
-1.95 V
DD
-1.61 V
V
SWING
Peak-to-Peak Output Voltage Swing 0.55 0.93 V
IDT5V49EE902
EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR 20
IDT5V49EE902 REV Q 071015
Power Supply Characteristics for LVPECL Outputs
1
Note 1: Output banks 4 and 5 are toggling. Other output banks are powered down.
Note 2: The termination resistors are excluded from these measurements.
DC Electrical Characteristics for HCSL
Power Supply Characteristics for HCSL Outputs
1
Note 1: Output banks 4 and 5 are toggling. Other output banks are powered down.
Note 2: The termination resistors are excluded from these measurements.
Symbol Parameter Test Conditions
2
Typ Max Unit
I
DDQ
Quiescent V
DD
Power
Supply Current
REF = LOW
Outputs enabled, all outputs unloaded
86 110 mA
I
DDD
Dynamic V
DD
Power Supply
Current per Output
V
DD
= Max., C
L
= 0pF 35 50 µA/MHz
I
TOT
Total Powe r V
DD
Supply
Current
F
REFERENCE CLOCK
= 100 MHz, C
L
= 2 pF 120 180 mA
F
REFERENCE CLOCK
= 200 MHz, C
L
= 2 pF 130 190
F
REFERENCE CLOCK
= 400 MHz, C
L
= 2 pF 140 210
Symbol Parameter Min Typ Max Unit
V
OH
Output Voltage HIGH 660 700 850 mV
V
OL
Output Voltage LOW -150 0 27 mV
Crossing
Point
Voltage
Absolute 250 350 550 mV
Symbol Parameter Test Conditions
2
Typ Max Unit
I
DDQ
Quiescent V
DD
Power
Supply Current
REF = LOW
Outputs enabled, all outputs unloaded
68 90 mA
I
DDD
Dynamic V
DD
Power Supply
Current per Output
V
DD
= Max., C
L
= 0pF 30 45 µA/MHz
I
TOT
Total Powe r V
DD
Supply
Current
F
REFERENCE CLOCK
= 100 MHz, C
L
= 2 pF 86 130 mA
F
REFERENCE CLOCK
= 200 MHz, C
L
= 2 pF 100 150
F
REFERENCE CLOCK
= 400 MHz, C
L
= 2 pF 122 190
IDT5V49EE902
EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR 21
IDT5V49EE902 REV Q 071015
AC Timing Electrical Characteristics
(Spread Spectrum Generation = OFF)
Symbol Parameter Test Conditions Min. Typ. Max. Units
f
IN
1
Input Frequency
Input frequency limit (CLKIN) 1 200 MHz
Input frequency limit (XIN/REF) 8 100 MHz
1 / t1 Output Frequency Single ended clock output limit (LVTTL) 0.001 200 MHz
Differential clock output limit (LVPECL/
LVDS/HCSL)
0.001 500
f
VCO
VCO Frequency VCO operating frequency range 100 1300 MHz
f
PFD
PFD Frequency PFD operating frequency range 0.5
1
100 MHz
f
BW
Loop Bandwidth Based on loop filter resistor and capacitor
values
0.01 10 MHz
t2 Input Duty Cycle Duty Cycle for input 40 60 %
t3 Output Duty Cycle Measured at V
DD
/2, all outputs except
Reference output
45 55 %
Measured at V
DD
/2, Reference output 40 60 %
t4
2
Slew Rate, SLEW[1:0] = 00 Single-ended 3.3V LVCMOS output clock rise
and fall time, 20% to 80% of V
DD
(Output Load = 5 pF)
3.5 V/ns
Slew Rate, SLEW[1:0] = 01 Single-ended 3.3V LVCMOS output clock rise
and fall time, 20% to 80% of V
DD
(Output Load = 5 pF)
2.75
Slew Rate, SLEW[1:0] = 10 Single-ended 3.3V LVCMOS output clock rise
and fall time, 20% to 80% of V
DD
(Output Load = 5 pF)
2
Slew Rate, SLEW[1:0] = 11 Single-ended 3.3V LVCMOS output clock rise
and fall time, 20% to 80% of V
DD
(Output Load = 5 pF)
1.25
t5 Rise Times LVDS, 20% to 80% 600 ps
Fall Times LVDS, 80% to 20% 600
Rise Times LVPECL, 20% to 80% 600 ps
Fall Times LVPECL, 80% to 20% 600
Rise Times HCSL, From 0.175 V to 0.525 V
175 400 700
ps
Fall Times HCSL, From 0.525 V to 0.175 V
175 400 700
t7 Clock Jitter
6
Peak-to-peak period jitter, 1PLL, multiple
output frequencies switching, LVTTL outputs
80 100 ps
Peak-to-peak period jitter, all 4 PLLs on,
LVTTL outputs
3
200 270 ps
Peak-to-peak period jitter, 1PLL, multiple
output frequencies switching, LVPECL, LVDS
or HCSL outputs
60 80 ps
Peak-to-peak period jitter, all 4 PLLs on,
LVPECL, LVDS or HCSL outputs
120 160 ps
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33

5V49EE902NLGI8

Mfr. #:
Buy 5V49EE902NLGI8
Manufacturer:
IDT
Description:
Clock Generators & Support Products EEPROM PROGRAMMABLE PLL
Lifecycle:
New from this manufacturer.
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