IDT5V49EE902
EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR 32
IDT5V49EE902 REV Q 071015
Revision History
Rev. Originator Date Description of Change
A R.Willner 4/22/09 Advance Information.
B R.Willner 5/04/09 Identified VDDX (crystal oscillator power) and AVDD (analog power) on device.
C R.Willner 6/04/09 Add default configurations, pull-down resistor values on input pins.
Released Datasheet from Advanced Information.
D R.Willner 06/10/09 Updates: crystal load specs; “Output Duty Cycle” specs; addresses 0x07, 0x02 and 0xBF
in “Programming Registers” table.
E R.Willner 08/26/09 Updated 32-pin VFQFPN thermal data.
F R.Willner 10/05/09 Changed IP3[3:0] to IP3[4:0]; updated “Programming Registers Table”.
G R.Willner 12/09/09 Increased Max VCO frequency to 1300 MHz
H R.Willner 02/23/10 Updated Recommended Operation Conditions to include Vddx and AVdd parameters.
J R.Willner 04/22/11 Added 32QFN Landing Pattern diagram.
K A. Tsui 07/07/11 Updated package dimension drawing
L R. Willner 04/17/12 1. Change description for SDAT and SCLK pins.
2. Add new footnotes to pin descriptions table
3. Added section "Crystal Clock Selection"
4. Added logic diagram and Truth table for "SD/OE Pin Function" section.
5. Corrected register readback values for 0x52~0x54 and 0x7C~0x7F.
6. Update to QFN package drawing - exposed thermal pad callout.
M A. Tsui 06/04/12 1. Updated SD-OE pin description; from (Default is active HIGH) to (Default is active
LOW)
2. Updated “OUTn” column in Truth Table with “High-Z” specs and added footnote 2,
“High-Z regardless of OEM bits”.
3. Updated “SD-OE Pin Function” section to reflect that SP is “0”changed from active
HIGH to active LOW, and SP is “1” changed from active LOW to active HIGH.
N R.Willner 06/18/12 Added Min/Max spread values to "Spread Spectrum Generation Specifications" table;
fMOD - Max. 120kHz; Down Spread - Min. -0.5%, Max. -4.0%; Center Spread - Min.
±0.25%, Max. ±2.0%
P R.Willner 09/24/12 Change differential outputs from 5pF loads to 2pF loads so that they are consistent with
the industry. Capacitive loads were also added to the test circuit diagrams for HCSL
outputs. Slew Rate (t4) Output Load test conditions were also changed from 15pF to 5pF.
Q A.B. 07/10/15 Added the following note under AC Timing Electrical Characteristics table:
“Not guaranteed until customer specific configuration is approved by IDT.”
