89HPES64H16ZABL Datasheet 89HPES64H16ZABR, 89HPES64H16ZABRI, 89HPES64H16ZABL | P4-P6

4 of 49 September 28, 2011

IDT 89HPES64H16 Data Sheet

Pin Description

The following tables lists the functions of the pins provided on the PES64H16. Some of the functions listed may be multiplexed onto the same pin.

The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)

level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Differ-

ential signals end with a suffix “N” or “P.” The differential signal ending in “P” is the positive portion of the differential pair and the differential signal

ending in “N” is the negative portion of the differential pair.

Signal Type Name/Description

PE0RP[3:0]

PE0RN[3:0]

I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for

port 0. Port 0 is the upstream port.

PE0TP[3:0]

PE0TN[3:0]

O PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pairs for

port 0. Port 0 is the upstream port.

PE1RP[3:0]

PE1RN[3:0]

I PCI Express Port 1 Serial Data Receive. Differential PCI Express receive pairs for

port 1. When port 0 is merged with port 1, these signals become port 0 receive pairs

for lanes 4 through 7.

PE1TP[3:0]

PE1TN[3:0]

O PCI Express Port 1 Serial Data Transmit. Differential PCI Express transmit pairs for

port 1. When port 0 is merged with port 1, these signals become port 0 transmit pairs

for lanes 4 through 7.

PE2RP[3:0]

PE2RN[3:0]

I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pairs for

port 2.

PE2TP[3:0]

PE2TN[3:0]

O PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pairs for

port 2.

PE3RP[3:0]

PE3RN[3:0]

I PCI Express Port 3 Serial Data Receive. Differential PCI Express receive pairs for

port 3. When port 2 is merged with port 3, these signals become port 2 receive pairs

for lanes 4 through 7.

PE3TP[3:0]

PE3TN[3:0]

O PCI Express Port 3 Serial Data Transmit. Differential PCI Express transmit pairs for

port 2. When port 2 is merged with port 3, these signals become port 2 transmit pairs

for lanes 4 through 7.

PE4RP[3:0]

PE4RN[3:0]

I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pairs for

port 4.

PE4TP[3:0]

PE4TN[3:0]

O PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit pairs for

port 4.

PE5RP[3:0]

PE5RN[3:0]

I PCI Express Port 5 Serial Data Receive. Differential PCI Express receive pairs for

port 5. When port 4 is merged with port 5, these signals become port 4 receive pairs

for lanes 4 through 7.

PE5TP[3:0]

PE5TN[3:0]

O PCI Express Port 5 Serial Data Transmit. Differential PCI Express transmit pairs for

port 5. When port 4 is merged with port 5, these signals become port 4 transmit pairs

for lanes 4 through 7.

PE6RP[3:0]

PE6RN[3:0]

I PCI Express Port 6 Serial Data Receive. Differential PCI Express receive pairs for

port 6.

PE6TP[3:0]

PE6TN[3:0]

O PCI Express Port 6 Serial Data Transmit. Differential PCI Express transmit pairs for

port 6.

PE7RP[3:0]

PE7RN[3:0]

I PCI Express Port 7 Serial Data Receive. Differential PCI Express receive pairs for

port 7. When port 6 is merged with port 7, these signals become port 6 receive pairs

for lanes 4 through 7.

PE7TP[3:0]

PE7TN[3:0]

O PCI Express Port 7 Serial Data Transmit. Differential PCI Express transmit pairs for

port 7. When port 6 is merged with port 7, these signals become port 6 transmit pairs

for lanes 4 through 7.

Table 2 PCI Express Interface Pins (Part 1 of 2)

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IDT 89HPES64H16 Data Sheet

PE8RP[3:0]

PE8RN[3:0]

I PCI Express Port 8 Serial Data Receive. Differential PCI Express receive pairs for

port 8.

PE8TP[3:0]

PE8TN[3:0]

O PCI Express Port 8 Serial Data Transmit. Differential PCI Express transmit pairs for

port 8.

PE9RP[3:0]

PE9RN[3:0]

I PCI Express Port 9 Serial Data Receive. Differential PCI Express receive pairs for

port 9. When port 8 is merged with port 9, these signals become port 8 receive pairs

for lanes 4 through 7.

PE9TP[3:0]

PE9TN[3:0]

O PCI Express Port 9 Serial Data Transmit. Differential PCI Express transmit pairs for

port 9. When port 8 is merged with port 9, these signals become port 8 transmit pairs

for lanes 4 through 7.

PE10RP[3:0]

PE10RN[3:0]

I PCI Express Port 10 Serial Data Receive. Differential PCI Express receive pairs for

port 10.

PE10TP[3:0]

PE10TN[3:0]

O PCI Express Port 10 Serial Data Transmit. Differential PCI Express transmit pairs

for port 10.

PE11RP[3:0]

PE11RN[3:0]

I PCI Express Port 11 Serial Data Receive. Differential PCI Express receive pairs for

port 11. When port 10 is merged with port 11, these signals become port 10 receive

pairs for lanes 4 through 7.

PE11TP[3:0]

PE11TN[3:0]

O PCI Express Port 11 Serial Data Transmit. Differential PCI Express transmit pairs

for port 11. When port 10 is merged with port 11, these signals become port 10 trans-

mit pairs for lanes 4 through 7.

PE12RP[3:0]

PE12RN[3:0]

I PCI Express Port 12 Serial Data Receive. Differential PCI Express receive pairs for

port 12.

PE12TP[3:0]

PE12TN[3:0]

O PCI Express Port 12 Serial Data Transmit. Differential PCI Express transmit pairs

for port 12.

PE13RP[3:0]

PE13RN[3:0]

I PCI Express Port 13 Serial Data Receive. Differential PCI Express receive pairs for

port 13. When port 12 is merged with port 13, these signals become port 12 receive

pairs for lanes 4 through 7.

PE13TP[3:0]

PE13TN[3:0]

O PCI Express Port 13 Serial Data Transmit. Differential PCI Express transmit pairs

for port 13. When port 12 is merged with port 13, these signals become port 12 trans-

mit pairs for lanes 4 through 7.

PE14RP[3:0]

PE14RN[3:0]

I PCI Express Port 14 Serial Data Receive. Differential PCI Express receive pairs for

port 14.

PE14TP[3:0]

PE14TN[3:0]

O PCI Express Port 14 Serial Data Transmit. Differential PCI Express transmit pairs

for port 14.

PE15RP[3:0]

PE15RN[3:0]

I PCI Express Port 15 Serial Data Receive. Differential PCI Express receive pairs for

port 15. When port 14 is merged with port 15, these signals become port 14 receive

pairs for lanes 4 through 7.

PE15TP[3:0]

PE15TN[3:0]

O PCI Express Port 15 Serial Data Transmit.

Differential PCI Express transmit pairs

for port 15. When port 14 is merged with port 15, these signals become port 14 trans-

mit pairs for lanes 4 through 7.

REFCLKM I PCI Express Reference Clock Mode Select. This signal selects the frequency of the

reference clock input.

0x0 - 100 MHz

0x1 - 125 MHz

PEREFCLKP[3:0]

PEREFCLKN[3:0]

I PCI Express Reference Clock. Differential reference clock pair input. This clock is

used as the reference clock by on-chip PLLs to generate the clocks required for the

system logic and on-chip SerDes. The frequency of the differential reference clock is

determined by the REFCLKM signal.

Signal Type Name/Description

Table 2 PCI Express Interface Pins (Part 2 of 2)

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IDT 89HPES64H16 Data Sheet

Signal Type Name/Description

MSMBADDR[4:1] I Master SMBus Address. These pins determine the SMBus address of the serial

EEPROM from which configuration information is loaded.

MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the

master SMBus. It is active and generating the clock only when the EEPROM or I/O

Expanders are being accessed.

MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the master SMBus.

SSMBADDR[5,3:1] I Slave SMBus Address. These pins determine the SMBus address to which the slave

SMBus interface responds.

SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the

slave SMBus.

SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus.

Table 3 SMBus Interface Pins

Signal Type Name/Description

GPIO[0] I/O General Purpose I/O.