NCP5211A
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10
APPLICATIONS INFORMATION
APPLICATIONS AND COMPONENT SELECTION
Inductor Component Selection
The output inductor may be the most critical component
in the converter because it will directly effect the choice of
other components and dictate both the steady−state and
transient performance of the converter. When selecting an
inductor, the designer must consider factors such as DC
current, peak current, output voltage ripple, core material,
magnetic saturation, temperature, physical size, and cost
(usually the primary concern).
In general, the output inductance value should be as low
and physically small as possible to provide the best transient
response and minimum cost. If a large inductance value is
used, the converter will not respond quickly to rapid changes
in the load current. On the other hand, too low an inductance
value will result in very large ripple currents in the power
components (MOSFETs, capacitors, etc.) resulting in
increased dissipation and lower converter efficiency.
Increased ripple currents will force the designer to use
higher rated MOSFETs, oversize the thermal solution, and
use more, higher rated input and output capacitors. The
converter cost will be adversely affected.
One method of calculating an output inductor value is to
size the inductor to produce a specified maximum ripple
current in the inductor. Lower ripple currents will result in
less core and MOSFET losses and higher converter
efficiency. The following equation may be used to calculate
the minimum inductor value to produce a given maximum
ripple current (α I
O,MAX
). The inductor value calculated by
this equation is a minimum because values less than this will
produce more ripple current than desired. Conversely,
higher inductor values will result in less than the maximum
ripple current.
Lo
MIN
(Vin Vout) Vout( I
O,MAX
Vin f
SW
)
α is the ripple current as a percentage of the maximum
output current (α = 0.15 for ±15%, α = 0.25 for ±25%, etc)
and f
sw
is the switching frequency. If the minimum inductor
value is used, the inductor current will swing ±α/2% about
Iout. Therefore, the inductor must be designed or selected
such that it will not saturate with a peak current of (1 + α/2)
I
O,MAX
.
Power dissipation in the inductor can now be calculated
from the RMS current level. The RMS of the ac component
of the inductor is given by the following relationship:
I
AC
I
PP
12
where IPP = α I
O,MAX
.
The total I
RMS
of the current will be calculated from:
I
RMS
I
OUT
2
I
AC
2
The power dissipation for the inductor can be determined
from:
P I
RMS
2
ESR
Input Capacitor Selection and Considerations
The input capacitor is used to reduce voltage ripple caused
by the current surges in the top pass transistor.
The input current is pulsing at the switching frequency
going from 0 to peak current in the inductor. The duty cycle
will be a function of the ratio of the input to output voltage
and of the efficiency.
D
V
O
V
I
1
Eff
The RMS value of the ripple into the input capacitors can
now be calculated:
I
IN(RMS)
I
OUT
D D
2
The input RMS is maximum at 50% D, so selection of the
possible duty cycle closest to 50% will give the worst case
dissipation in the capacitors. The power dissipation of the
input capacitors can be calculated by multiplying the square
of the RMS current by the ESR of the capacitor.
Output Capacitor
The output capacitor filters output inductor ripple current
and provides low impedance for load current changes. The
effect of the capacitance for handling the power supply
induced ripple will be discussed here. Effects of load
transient behavior can be considered separately.
The principle consideration for the output capacitor is the
ripple current induced by the switches through the inductor.
This ripple current was calculated as I
AC
in the above
discussion of the inductor. This ripple component will
induce heating in the capacitor by a factor of the RMS
current squared multiplied by the ESR of the output
capacitor section. It will also create output ripple voltage.
The ripple voltage will be a vector summation of the ripple
current times the ESR of the capacitor, plus the ripple current
integrating in the capacitor, and the rate of change in current
times the total series inductance of the capacitor and
connections.
The inductor ripple current acting against the ESR of the
output capacitor is the major contributor to the output ripple
voltage. This fact can be used as a criterion to select the
output capacitor.
V
PP
I
PP
C
ESR
The power dissipation in the output capacitor can be
calculated from:
P I
AC
2
C
ESR
where:
I
AC
= ac RMS current
C
ESR
= Effective series resistance of the output capacitor
network.
MOSFET & Heatsink Selection
Power dissipation, package size, and thermal solution
drive MOSFET selection. To adequately size the heat sink,
the design must first predict the MOSFET power dissipation.
NCP5211A
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11
Once the dissipation is known, the heat sink thermal
impedance can be calculated to prevent the specified
maximum case or junction temperatures from being exceeded
at the highest ambient temperature. Power dissipation has two
primary contributors: conduction losses and switching losses.
The control or upper MOSFET will display both switching
and conduction losses. The synchronous or lower MOSFET
will exhibit only conduction losses because it switches into
nearly zero voltage. However, the body diode in the
synchronous MOSFET will suffer diode losses during the
non−overlap time of the gate drivers.
For the upper or control MOSFET, the power dissipation
can be approximated from:
P
D,CONTROL
(I
RMS,CNTL
2
R
DS(on)
)
(I
Lo,MAX
Q
switch
I
g
V
IN
f
SW
)
(Q
oss
2 V
IN
f
SW
) (V
IN
Q
RR
f
SW
)
The first term represents the conduction or IR losses when
the MOSFET is ON while the second term represents the
switching losses. The third term is the losses associated with
the control and synchronous MOSFET output charge when
the control MOSFET turns ON. The output losses are caused
by both the control and synchronous MOSFET but are
dissipated only in the control FET. The fourth term is the loss
due to the reverse recovery time of the body diode in the
synchronous MOSFET. The first two terms are usually
adequate to predict the majority of the losses.
Where I
RMS,CNTL
is the RMS value of the trapezoidal
current in the control MOSFET:
I
RMS,CNTL
D
[(I
Lo,MAX
2
I
Lo,MAX
I
Lo,MIN
I
Lo,MIN
2
)3]
12
I
Lo,MAX
is the maximum output inductor current:
I
Lo,MAX
I
O,MAX
2 I
Lo
2
I
Lo,MIN
is the minimum output inductor current:
I
Lo,MIN
I
O,MAX
2 I
Lo
2
I
O,MAX
is the maximum converter output current.
D is the duty cycle of the converter:
D V
OUT
V
IN
I
Lo
is the peak−to−peak ripple current in the output
inductor of value Lo:
I
Lo
(V
IN
V
OUT
) D(Lo f
SW
)
R
DS(on)
is the ON resistance of the MOSFET at the
applied gate drive voltage.
Q
switch
is the post gate threshold portion of the
gate−to−source charge plus the gate−to−drain charge. This
may be specified in the data sheet or approximated from the
gate−charge curve as shown in the Figure 13.
Q
switch
Q
gs2
Q
gd
I
D
V
GATE
V
DRAIN
Q
GD
Q
GS2
Q
GS1
V
GS_TH
Figure 13. MOSFET Switching Characteristics
I
g
is the output current from the gate driver IC.
V
IN
is the input voltage to the converter.
f
sw
is the switching frequency of the converter.
Q
G
is the MOSFET total gate charge to obtain R
DS(on)
(commonly specified in the data sheet).
V
g
is the gate drive voltage.
Q
RR
is the reverse recovery charge of the lower MOSFET.
Q
oss
is the MOSFET output charge specified in the data
sheet.
For the lower or synchronous MOSFET, the power
dissipation can be approximated from:
P
D,SYNCH
(I
RMS,SYNCH
2
R
DS(on)
)
(Vf
diode
I
O,MAX
2 t_nonoverlap f
SW
)
The first term represents the conduction or IR losses when
the MOSFET is ON and the second term represents the diode
losses that occur during the gate non−overlap time.
All terms were defined in the previous discussion for the
control MOSFET with the exception of:
I
RMS,SYNCH
1 D
[(I
Lo,MAX
2
I
Lo,MAX
I
Lo,MIN
I
Lo,MIN
2
)3]
12
where:
Vf
diode
is the forward voltage of the MOSFET’s intrinsic
diode at the converter output current.
t_nonoverlap is the non−overlap time between the upper
and lower gate drivers to prevent cross conduction. This
time is usually specified in the data sheet for the control
IC.
When the MOSFET power dissipations are known, the
designer can calculate the required thermal impedance to
maintain a specified junction temperature at the worst case
ambient operating temperature
T
(T
J
T
A
)P
D
where;
θ
T
is the total thermal impedance (θ
JC
+ θ
SA
).
NCP5211A
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12
θ
JC
is the junction−to−case thermal impedance of the
MOSFET.
θ
SA
is the sink−to−ambient thermal impedance of the
heatsink assuming direct mounting of the MOSFET (no
thermal “pad” is used).
T
J
is the specified maximum allowed junction
temperature.
T
A
is the worst case ambient operating temperature.
For TO−220 and TO−263 packages, standard FR−4
copper clad circuit boards will have approximate thermal
resistances (θ
SA
) as shown below:
Pad Size
(in
2
/mm
2
)
Single−Sided
1 oz. Copper
0.5/323 60−65°C/W
0.75/484 55−60°C/W
1.0/645 50−55°C/W
1.5/968 45−50°C/W
2.0/1290 38−42°C/W
2.5/1612 33−37°C/W
As with any power design, proper laboratory testing
should be performed to insure the design will dissipate the
required power under worst case operating conditions.
Variables considered during testing should include
maximum ambient temperature, minimum airflow,
maximum input voltage, maximum loading, and component
variations (i.e. worst case MOSFET R
DS(on)
). Also, the
inductors and capacitors share the MOSFET’s heatsinks and
will add heat and raise the temperature of the circuit board
and MOSFET. For any new design, it is advisable to have as
much heatsink area as possible. All too often, new designs
are found to be too hot and require re−design to add
heatsinking.
Compensation Capacitor Selection
The nominal output current capability of the error amp is
30 µA. This current charging the capacitor on the COMP pin
is used as soft start for the converter. The COMP pin will
ramp up to a voltage level within 55 mV of what V
FFB
will
be when in regulation. This is the voltage that will determine
the soft start. Therefore, the COMP capacitor can be
established by the following relationship:
C 30 A
soft start
V
FFB(REG)
where:
soft start = output ramp−up time
V
FFB(REG)
= V
FFB
voltage when in regulation
30 µA = COMP output current, typ.
The COMP output current range is given in the data sheet
and will affect the ramp−up time. The value of the capacitor
on the COMP pin will have an effect on the loop response
and the transient response of the converter. Transient
response can be enhanced by the addition of a parallel
combination of a resistor and capacitor between the COMP
pin and the comp capacitor.
R
OSC
Selection
The switching frequency is programmed by selecting the
resistor connected between the R
OSC
pin and SGND (pin 7).
The grounded side of this resistor should be directly
connected to the SGND pin, without any other currents
flowing between the bottom of the resistor and the pin. Also,
avoid running any noisy signals under the resistor, since
injected noise could cause frequency jitter. The graph in
Figure 6 shows the required resistance to program the
frequency.
Differential Remote Sense Operation
The ability to implement fully differential remote sense is
provided by the NCP5211A. The positive remote sense is
implemented by bringing the output remote sense
connection to the positive load connection. A low value
resistor is connected from Vout to the feedback point at the
regulator to provide feedback in the instance when the
remote sense point is not connected.
The negative remote sense connection is provided by
connecting the SGND of the NCP5211A to the negative of
the load return. Again, a low value resistor should be
connected between SGND and LGND at the regulator to
provide feedback in the instance when the remote sense
point is not connected. The maximum voltage differential
between the three grounds for this part is 200 mV.
Feedback Divider Selection
The feedback voltage measured at V
FB
during normal
regulation will be 0.8 V. This voltage is compared to an
internal 0.8 V reference and is used to regulate the output
voltage. The bias current into the error amplifier is 1.0 µA
maximum, so select the resistor values so that this current
does not add an excessive offset voltage.
V
FFB
Feedback Selection
To take full advantage of the V
2
control scheme, a small
amount of output ripple is fed back to the V
FFB
pin. For most
applications, the V
FFB
pin can be connected directly to the
V
FB
pin. There are some applications that have to meet
stringent load transient requirements. One of the key factors
in achieving tight dynamic voltage regulation is low output
capacitor ESR. Low ESR results in low output voltage
ripple. This situation could result in increased noise
sensitivity and a potential for loop instability. In applications
where the output ripple is not sufficient, the performance of
the NCP5211A can be improved by adding a fixed amount
of external ramp compensation to the V
FFB
pin. Figure 14
shows how the amount of ramp at the V
FFB
pin depends on
the switch node voltage, feedback voltage, R1 and C2.
Vramp (Vsw V
FB
) ton(R1 C2)

NCP5211ADR2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC REG CTRLR BUCK 14SOIC
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