MAX7323ATE+ Datasheet MAX7323AEE+, MAX7323ATE+, MAX7323AEE+T | P7-P9

Slave Address and Input Pullup Selection

Address inputs AD0 and AD2 determine the MAX7323

slave address, select which inputs have pullup resis-

tors, and set the default logic state on outputs. Pullups

are enabled on the input ports in groups of two (see

Table 3). The MAX7319, MAX7321, MAX7322, and

MAX7323 use a different range of slave addresses

(110xxxx) than the MAX7320 (101xxxx).

The MAX7323 slave address is determined on each I

transmission, regardless of whether the transmission is

actually addressing the MAX7323. The MAX7323 distin-

guishes whether address inputs AD2 and AD0 are con-

nected to SDA or SCL instead of fixed logic levels V+ or

GND during this transmission. Therefore, the MAX7323

slave address can be configured dynamically in the

application without cycling the device supply.

On initial power-up, the MAX7323 cannot decode

address inputs AD2 and AD0 fully until the first I

transmission. AD0 and AD2 initially appear to be con-

nected to V+ or GND. This is important because the

address selection determines the power-up default

states of the output ports and I/O port initial logic state,

and whether pullups are enabled. However, at power-

up, the I

C SDA and SCL bus interface lines are high

impedance at the pins of every device (master or slave)

connected to the bus, including the MAX7323. This is

guaranteed as part of the I

C specification. Therefore,

address inputs AD2 and AD0 that are connected to

SDA or SCL normally appear at power-up to be con-

nected to V+. The pullup selection logic uses AD0 to

select whether pullups are enabled for ports P2 and P3,

and to set the initial logic state for O0 and O1. AD2

selects whether pullups are enabled for ports P4 and

P5 and sets the initial logic state for O6 and O7. The

rule is that a logic-high, SDA, or SCL connection

selects the pullups and sets the default logic state to

high. A logic-low deselects the pullups and sets the

default logic state low (see Table 3). The port configu-

ration is correct on power-up for a standard I

C config-

uration, where SDA or SCL are pulled up to V+ by the

external I

C pullup resistors.

There are circumstances where the assumption that

SDA = SCL = V+ on power-up is not true—for example,

in applications in which there is legitimate bus activity

during power-up. Also, if SDA and SCL are terminated

with pullup resistors to a different supply voltage than

the MAX7323’s supply voltage, and if that pullup supply

rises later than the MAX7323’s supply, then SDA or SCL

may appear at power-up to be connected to GND. In

such applications, use the four address combinations

that are selected by connecting address inputs AD2

MAX7323

C Port Expander with 4 Push-Pull Outputs

and 4 Open-Drain I/Os

_______________________________________________________________________________________ 7

PART

C SLAVE

ADDRESS

INPUTS

INTERRUPT

MASK

OPEN-

DRAIN

OUTPUTS

PUSH-

PULL

OUTPUTS

C DATA WRITE I

C DATA READ

MAX7319 110xxxx 8 Yes — —

<I7–I0 interrupt

mask>

<I7–I0 port inputs>

<I7–I0 transition flags>

MAX7320 101xxxx — — — 8

<O7–O0 port

outputs>

<O7-O0 port inputs>

MAX7321 110xxxx Up to 8 — Up to 8 —

<P7–P0 port

outputs>

<P7–P0 port inputs>

<P7–P0 transition flags>

MAX7322 110xxxx 4 Yes — 4

<O7, O6 outputs,

I5–I2 interrupt

mask, O1, O0

outputs>

<O7, O6, I5–I2, O1, O0 port

inputs>

<0, 0, I5–I2 transition flags,

0, 0>

MAX7323 110xxxx Up to 4 — Up to 4 4 <port outputs>

<O7, O6, P5–P2, O1, O0 port

inputs>

<0, 0, P5–P2 transition flags,

0, 0>

MAX7328 0100xxx Up to 8 — Up to 8 —

<P7–P0 port

outputs>

<P7–P0 port inputs>

MAX7329 0111xxx Up to 8 — Up to 8 —

<P7–P0 port

outputs>

<P7–P0 port inputs>

Table 2. Read and Write Access to Eight-Port Expander Family

MAX7323

and AD0 to V+ or GND (shown in bold in Table 3).

These selections are guaranteed to be correct at

power-up, independent of SDA and SCL behavior. If

one of the other 12 address combinations is used, an

unexpected combination of pullups might be asserted

until the first I

C transmission (to any device, not neces-

sarily the MAX7323) is put on the bus.

I/O Port Inputs

I/O port inputs switch at the CMOS logic levels as

determined by the expander’s supply voltage, and are

overvoltage tolerant to +6V, independent of the

expander’s supply voltage.

I/O Port Input Transition Detection

All four I/O ports configured as inputs are monitored for

changes since the expander was last accessed

through the serial interface. The state of the I/O ports is

stored in an internal “snapshot” register for transition

monitoring. The snapshot is continuously compared

with the actual input conditions, and if a change is

detected for any port input, INT is asserted to signal a

state change. An internal transition flag is set for that

port. The input ports are sampled (internally latched

into the snapshot register) and the old transition flags

cleared during the I

C acknowledge of every MAX7323

read and write access. The previous port transition

flags are read through the serial interface as the sec-

ond byte of a 2-byte read sequence.

A long read sequence (more than 2 bytes) can be used

to poll the expander continuously without the overhead

of resending the slave address. If more than 2 bytes

are read from the expander, the expander repeatedly

returns the input port data, alternating with the transition

flags. The inputs are repeatedly resampled and the

transition flags repeatedly reset for each pair of bytes

read. All changes that occur during a long read

sequence are detected and reported.

The INT output is not reasserted during a read

sequence to avoid recursive reentry into an interrupt

service routine. Instead, if a data change occurs that

would normally cause the INT output to be set, the INT

assertion is delayed until the STOP condition. INT is not

reasserted upon a STOP condition if the changed input

data is read before the STOP occurs. The INT logic

ensures that unnecessary interrupts are not asserted,

yet data changes are detected and reported no matter

when the change occurs.

Port Outputs

Write 1 byte to the MAX7323 to set the output port lev-

els for the four push-pull outputs, and the four open-

drain I/O ports simultaneously.

C Port Expander with 4 Push-Pull Outputs

and 4 Open-Drain I/Os

8 _______________________________________________________________________________________

CONNECTION

DEVICE ADDRESS OUTPUTS POWER-UP DEFAULT

40kΩ INPUT PULLUPS ENABLED

AD2 AD0 A6 A5 A4 A3 A2 A1 A0 O7 O6 P5 P4 P3 P2 O1 O0 O7 O6 P5 P4 P3 P2 O1 O0

SCL GND110000011110000 YY——

SCL V+ 110000111111111 YYYY

SCL SCL 110001011111111 YYYY

SCL SDA 110001111111111 YYYY

SDAGND110010011110000 YY——

SDA V+ 110010111111111 YYYY

SDA SCL 110011011111111 YYYY

SDA SDA 110011111111111 YYYY

GNDGND110100000000000 ————

GND V+ 110100100001111 ——YY

GND SCL 110101000001111 ——YY

GNDSDA 110101100001111 ——YY

V+ GND110110011110000 YY——

V+ V+ 110110111111111 YYYY

V+ SCL 110111011111111 YYYY

V+ SDA110111111111111

Pullups are not enabled for push-pull outputs.

YYYY

Pullups are not enabled for push-pull outputs.

Table 3. MAX7323 Address Map

Serial Interface

Serial Addressing

The MAX7323 operates as a slave that sends and

receives data through an I

C interface. The interface

uses a serial data line (SDA) and a serial clock line (SCL)

to achieve bidirectional communication between

master(s) and slave(s). The master initiates all data trans-

fers to and from the MAX7323 and generates the SCL

clock that synchronizes the data transfer (Figure 1).

SDA operates as both an input and an open-drain out-

put. A pullup resistor, typically 4.7kΩ, is required on

SDA. SCL operates only as an input. A pullup resistor,

typically 4.7kΩ, is required on SCL if there are multiple

masters on the 2-wire interface, or if the master in a sin-

gle-master system has an open-drain SCL output.

Each transmission consists of a START condition sent

by a master, followed by the MAX7323’s 7-bit slave

address plus R/W bit, 1 or more data bytes, and finally

a STOP condition (Figure 2).

START and STOP Conditions

Both SCL and SDA remain high when the interface is

not busy. A master signals the beginning of a transmis-

sion with a START (S) condition by transitioning SDA

from high to low while SCL is high. When the master

has finished communicating with the slave, the master

issues a STOP (P) condition by transitioning SDA from

low to high while SCL is high. The bus is then free for

another transmission (Figure 2).

Bit Transfer

One data bit is transferred during each clock pulse.

The data on SDA must remain stable while SCL is high

(Figure 3).

Acknowledge

The acknowledge bit is a clocked 9th bit the recipient

uses to acknowledge receipt of each byte of data

(Figure 4). Each byte transferred effectively requires 9

bits. The master generates the 9th clock pulse, and the

recipient pulls down SDA during the acknowledge

clock pulse, such that the SDA line is stable low during

the high period of the clock pulse. When the master is

transmitting to the MAX7323, the device generates the

acknowledge bit because the MAX7323 is the recipient.

When the MAX7323 is transmitting to the master, the

master generates the acknowledge bit because the

master is the recipient.

Slave Address

The MAX7323 has a 7-bit-long slave address (Figure

5). The 8th bit following the 7-bit slave address is the

R/W bit. It is low for a write command, and high for a

read command.

The first (A6), second (A5), and third (A4) bits of the

MAX7323 slave address are always 1, 1, and 0.

Connect AD2 and AD0 to GND, V+

SDA, or SCL to

select slave address bits A3, A2, A1, and A0. The

MAX7323 has 16 possible slave addresses (Table 3),

allowing up to 16 MAX7323 devices on an I

C bus.

MAX7323

C Port Expander with 4 Push-Pull Outputs

and 4 Open-Drain I/Os

_______________________________________________________________________________________ 9

SCL

SDA

BUF

START

CONDITION

STOP

CONDITION

REPEATED START CONDITION

START CONDITION

SU,STO

HD,STA

SU,STA

HD,DAT

SU,DAT

LOW

HIGH

HD,STA

Figure 1. 2-Wire Serial Interface Timing Details

SDA

SCL

START

CONDITION

STOP

CONDITION

Figure 2. START and STOP Conditions

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

MAX7323ATE+

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