NCV7519, NCV7519A
www.onsemi.com
10
Note: Not defined but usually MSB of data just received.
CSB
SETUP
CSB
SCLK
SI
SO
MSB IN LSB IN
MSB OUT
LSB OUT
SEE
NOTE
TRANSFER
DELAY
1
BITS 14...1
BITS 14...1
16
SO
DELAY
SI
SETUP
SI
HOLD
CSB
HOLD
SO
RISE,FALL
80% V
DD
20% V
DD
CSB to
SO VALID
Figure 9. SPI Timing Diagram
DETAILED OPERATING DESCRIPTION
General
The NCV7519 is a six channel general−purpose low−side
pre−driver for controlling and protecting N−type logic level
MOSFETs. Programmable fault detection and protection
modes allow the device to accommodate a wide range of
external MOSFETs and loads, providing flexible
application solutions. Separate power supply pins are
provided for low and high current paths to improve analog
accuracy and digital signal integrity.
Power Up/Down Control
An internal Power−On Reset (POR) monitors V
CC1
and
causes all GAT
X
outputs to be held low until sufficient
voltage is available to allow proper control of the device. All
internal registers are initialized to their defaults, status data
is cleared, and the open−drain fault flag (FLTB) is disabled.
When V
CC1
exceeds the POR threshold, the device is
initialized and ready to accept input data. When V
CC1
falls
below the POR threshold during power down, FLTB is
disabled and all GAT
X
outputs are driven and held low until
V
CC1
falls below about 1.5 V.
RSTB and ENB Inputs
The active−low RSTB input with a resistive pull−down
allows device reset by an external signal. When RSTB is
brought low, all GAT
X
outputs, the timer clock, the SPI, and
the FLTB flag are disabled. All internal registers are
initialized to their default states, status data is cleared, and
the SPI and FLTB are enabled when RSTB goes high.
The active−low ENB input with resistive pull−up
provides a global enable. ENB disables all GAT
X
outputs
and diagnostics, and resets the auto−retry timer when
brought high. The SPI is enabled, fault data is not cleared
and registers remain as programmed. Faulted outputs are
re−enabled when ENB goes low.
SPI Communication
The NCV7519 is a 16−bit slave device. Communication
between the host and the device may either be parallel via
individual CSB addressing or daisy−chained through other
devices using a compatible SPI protocol.
The active−low CSB chip select input has a pull−up
resistor. The SI and SCLK inputs have pull−down resistors.
The recommended idle state for SCLK is low. The tri−state
SO line driver is powered via the V
DD
and the V
SS
pins, and
can be supplied with either 3.3 V or 5 V.
The device employs odd parity, and frame error detection
that requires integer multiples of 16 SCLK cycles during
each CSB high−low−high cycle (valid communication
frame.) A parity or frame error does not affect the FLTB flag.
The host initiates communication when a selected
device’s CSB pin goes low. Output data is simultaneously
sent MSB first from the SO pin while input data is received
MSB first at the SI pin under synchronous control of the
master’s SCLK signal while CSB is held low (Figure 10).
Output data changes on the falling edge of SCLK and is
guaranteed valid before the next rising edge of SCLK. Input
data received must be valid before the rising edge of SCLK.
