...................... DOC #: SP-AP-0052 (Rev. AA) Page 11 of 31
3 0 Reserved Reserved
2 0 Reserved Reserved
1 1 25M0_F_OE Output enable for 25M0_F
0 = Output Disabled, 1 = Output Enabled
0 1 25M1_24.576M_OE Output enable for 25M1_24.576M
0 = Output Disabled, 1 = Output Enabled
Byte 8: Control Register 8 (continued)
Bit @Pup Name Description
Byte 9: Control Register 9
Bit @Pup Name Description
7 0 PCIF5_STP_CTRL Allows control of PCIF5 with assertion of PCI_STOP#
0 = Free running PCIF, 1 = Stopped with PCI_STOP#
6 0 Reserved Reserved
5 1 REF Bit1 REF drive strength Setting 1 of 3
(see Byte 13 and 14 for more settings)
0 = Low, 1 = High
4 0 TEST _MODE_SEL Test mode select either REF/N or tri-state
0 = All outputs tri-state, 1 = All output REF/N
3 0 TEST_MODE_ENTRY Allows entry into test mode
0 = Normal Operation, 1 = Enter test mode(s)
2 1 12C_VOUT<2> I2C_VOUT[2:0]
000 = 0.30V
001 = 0.40V
010 = 0.50V
011 = 060V
100 = 0.70V
101 = 0.80V (default)
110 = 0.90V
111 = 1.00V
1 0 12C_VOUT<1>
0 1 12C_VOUT<0>
Byte 10: Control Register 10
Bit @Pup Name Description
7 HW SRC5_EN SRC5_EN latche status
0= CPU_STP#/PCI_STP#; 1= SRC5
6 0 Reserved Reserved
5 0 Reserved Reserved
4 0 Reserved Reserved
3 0 Reserved Reserved
2 0 Reserved Reserved
1 1 CPU1_STP_CTRL Enable CPU_STOP# control of CPU1
0 = Free running, 1= Stoppable
0 1 CPU0_STP_CTRL Enable CPU_STOP# control of CPU0
0 = Free running, 1= Stoppable
Byte 11: Control Register 11
Bit @Pup Name Description
7 0 Reserved Reserved
6 0 Reserved Reserved
5 1 25M0_F 25M0_F Output Enabled applies to Powerdown / M1
0 = 25MHz disabled in Powerdown / M1
1 = 25MHz enabled in Powerdown / M1; Sticky 1
