1. General description
The 74ABT574A high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT574A is an 8-bit, edge triggered register coupled to eight 3-State output
buffers. The clock input (CP) and output enable input (OE
) control gates, control the two
sections of the device independently. The state of each data input (Dn, one set-up time
before the Low-to-High clock transition) is transferred to the Q output of the corresponding
flip-flop.
When OE
is Low, the stored data appears at the outputs. When OE is High, the outputs
are in the High-impedance “off” state, which means they do not drive or load the bus.
The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS
memories, or MOS microprocessors. The active-Low Output Enable (OE
) controls all
eight 3-State buffers independent of the clock operation.
2. Features and benefits
74ABT574A is flow-through pinout version of 74ABT374A
Inputs and outputs on opposite side of package allow easy
interface to microprocessors
3-State outputs for bus interfacing
Power-on 3-state
Power-on reset
Common output enable
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Live insertion/extraction permitted.
74ABT574A
Octal D-type flip-flop; 3-state
Rev. 2 — 23 November 2012 Product data sheet
74ABT574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 23 November 2012 2 of 16
NXP Semiconductors
74ABT574A
Octal D-type flip-flop; 3-state
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74ABT574AN 40 Cto+85C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
74ABT574AD 40 Cto+85C SO20 plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74ABT574ADB 40 Cto+85C SSOP20 plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
74ABT574APW 40 Cto+85C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
Fig 1. Logic symbol Fig 2. IEC logic symbol
mna798
D0
D1
D2
D3
D4
D5
D6
D7
OE
CP
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
11
1
12
13
14
15
16
17
18
19
9
8
7
6
5
4
3
2
mna446
12
13
14
15
16
17
18
11
C1
1
EN
1D
19
9
8
7
6
5
4
3
2
Fig 3. Logic diagram
001aah077
D0
CP
OE
Q0
D
CP
Q
FF1
D1
Q1
D
CP
Q
FF2
D2
Q2
D
CP
Q
FF3
D3
Q3
D
CP
Q
FF4
D4
Q4
D
CP
Q
FF5
D5
Q5
D
CP
Q
FF6
D6
Q6
D
CP
Q
FF7
D7
Q7
D
CP
Q
FF8
74ABT574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 23 November 2012 3 of 16
NXP Semiconductors
74ABT574A
Octal D-type flip-flop; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 4. Pin configuration DIP20 and SO20 Fig 5. Pin configuration SSOP20 and TSSOP20
2
(
9
&&
'
4
'
4
'
4
'
4
'
4
'
4
'
4
'
4
*1
'
&3











$%7 $
DDD
DDD
2
(
9
&&
'
4
'
4
'
4
'
4
'
4
'
4
'
4
'
4
*1
'
&3











$%7 $
Table 2. Pin description
Symbol Pin Description
OE
1 3-state output enable input (active LOW)
D0, D1, D2, D3, D4, D5, D6, D7 2, 3, 4, 5, 6, 7, 8, 9 data input
GND 10 ground (0 V)
CP 11 clock pulse input (active rising edge)
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 19, 18, 17, 16, 15, 14, 13, 12 3-state flip-flop output
V
CC
20 supply voltage

74ABT574APW,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC FF D-TYPE SNGL 8BIT 20TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union