74ABT574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 23 November 2012 7 of 16
NXP Semiconductors
74ABT574A
Octal D-type flip-flop; 3-state
11. Waveforms
V
M
= 1.5 V
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 6. Propagation delay clock input (CP) to output (Qn), clock pulse (CP) width and maximum clock (CP)
frequency
001aac445
CP
input
Qn
output
t
PHL
t
PLH
t
WH
t
WL
1 / f
max
V
M
V
OH
V
I
GND
V
OL
V
M
V
M
= 1.5 V
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 7. Set-up and hold times data output (Dn) to clock (CP)
74ABT574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 23 November 2012 8 of 16
NXP Semiconductors
74ABT574A
Octal D-type flip-flop; 3-state
V
M
= 1.5 V
V
OL
and V
OH
are typical voltage output levels that occur with the output load
Fig 8. 3-state output (Qn) enable and disable times
001aac448
t
PZL
Qn output
Qn output
OE input
V
OL
V
OH
V
I
V
M
GND
3.5 V
GND
t
PLZ
t
PZH
t
PHZ
V
OL
+
0.3 V
V
OH
0.3 V
V
M
V
M
a. Input pulse definition b. Test circuit
Test data is given in Table 8.
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
V
EXT
= External voltage for measuring switching times.
Fig 9. Test circuit for measuring switching times
001aai298
V
M
V
M
t
W
t
W
10 %
90 % 90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
90 %
10 % 10 %
t
f
t
r
t
r
t
f
V
EXT
V
CC
V
I
V
O
mna616
DUT
C
L
R
T
R
L
R
L
G
Table 8. Test data
Input Load V
EXT
V
I
f
i
t
W
t
r
, t
f
C
L
R
L
t
PHL
, t
PLH
t
PZH
, t
PHZ
t
PZL
, t
PLZ
3.0 V 1 MHz 500 ns 2.5 ns 50 pF 500 open open 7.0 V
74ABT574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 23 November 2012 9 of 16
NXP Semiconductors
74ABT574A
Octal D-type flip-flop; 3-state
12. Package outline
Fig 10. Package outline SOT146-1 (DIP20)
UNIT
A
max.
1 2
b
1
cD E e M
H
L
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT146-1
99-12-27
03-02-13
A
min.
A
max.
b
Z
max.
w
M
E
e
1
1.73
1.30
0.53
0.38
0.36
0.23
26.92
26.54
6.40
6.22
3.60
3.05
0.2542.54 7.62
8.25
7.80
10.0
8.3
24.2 0.51 3.2
0.068
0.051
0.021
0.015
0.014
0.009
1.060
1.045
0.25
0.24
0.14
0.12
0.010.1 0.3
0.32
0.31
0.39
0.33
0.0780.17 0.02 0.13
SC-603MS-001
M
H
c
(e )
1
M
E
A
L
seating plane
A
1
w M
b
1
e
D
A
2
Z
20
1
11
10
b
E
pin 1 index
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
(1)
(1) (1)
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1

74ABT574APW,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC FF D-TYPE SNGL 8BIT 20TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
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