CY7C027V/028V
CY7C037V/038V
6
Switching Characteristics
Over the Operating Range
[11]
Parameter Description
CY7C027V/028V
CY7C037V/038V
Unit
-15 -20 -25
Min. Max. Min. Max. Min. Max.
READ CYCLE
t
RC
Read Cycle Time 15 20 25 ns
t
AA
Address to Data Valid 15 20 25 ns
t
OHA
Output Hold From Address Change 3 3 3 ns
t
ACE
[12]
CE LOW to Data Valid 15 20 25 ns
t
DOE
OE LOW to Data Valid 10 12 13 ns
t
LZOE
[13, 14, 15]
OE LOW to Low Z 3 3 3 ns
t
HZOE
[13, 14, 15]
OE HIGH to High Z 10 12 15 ns
t
LZCE
[13, 14, 15]
CE LOW to Low Z 3 3 3 ns
t
HZCE
[13, 14, 15]
CE HIGH to High Z 10 12 15 ns
t
PU
[15]
CE LOW to Power-Up 0 0 0 ns
t
PD
[15]
CE HIGH to Power-Down 15 20 25 ns
t
ABE
[12]
Byte Enable Access Time 15 20 25 ns
WRITE CYCLE
t
WC
Write Cycle Time 15 20 25 ns
t
SCE
[12]
CE LOW to Write End 12 16 20 ns
t
AW
Address Valid to Write End 12 16 20 ns
t
HA
Address Hold From Write End 0 0 0 ns
t
SA
[12]
Address Set-Up to Write Start 0 0 0 ns
t
PWE
Write Pulse Width 12 17 22 ns
t
SD
Data Set-Up to Write End 10 12 15 ns
t
HD
Data Hold From Write End 0 0 0 ns
t
HZWE
[14, 15]
R/W LOW to High Z 10 12 15 ns
t
LZWE
[14 ,15]
R/W HIGH to Low Z 3 3 3 ns
t
WDD
[16]
Write Pulse to Data Delay 30 40 50 ns
t
DDD
[16]
Write Data Valid to Read Data Valid 25 30 35 ns
BUSY TIMING
[17]
t
BLA
BUSY LOW from Address Match 15 20 20 ns
t
BHA
BUSY HIGH from Address Mismatch 15 20 20 ns
t
BLC
BUSY LOW from CE LOW 152020ns
t
BHC
BUSY HIGH from CE HIGH 15 16 17 ns
t
PS
Port Set-Up for Priority 5 5 5 ns
t
WB
R/W HIGH after BUSY (Slave) 0 0 0 ns
t
WH
R/W HIGH after BUSY HIGH (Slave) 13 15 17 ns
t
BDD
[18]
BUSY HIGH to Data Valid 15 20 25 ns
Notes:
11. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OI
/I
OH
and 30-pF load capacitance.
12. To access RAM, CE
=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire t
SCE
time.
13. At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
14. Test conditions used are Load 2.
15. This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading
port, refer to Read Timing with Busy waveform.
16. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
17. Test conditions used are Load 1.
18. t
BDD
is a calculated parameter and is the greater of t
WDD
–t
PWE
(actual) or t
DDD
–t
SD
(actual).
