CY7C027V/028V
CY7C037V/038V
9
Notes:
25. R/W
must be HIGH during all address transitions.
26. A write occurs during the overlap (t
SCE
or t
PWE
) of a LOW CE or SEM and a LOW UB or LB.
27. t
HA
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
28. If OE
is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
PWE
or (t
HZWE
+ t
SD
) to allow the I/O drivers to turn off and data to be placed on
the bus for the required t
SD
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
PWE
.
29. To access RAM, CE
= V
IL
, SEM = V
IH
.
30. To access upper byte, CE
= V
IL
, UB = V
IL
, SEM = V
IH
.
To access lower byte, CE
= V
IL
, LB = V
IL
, SEM = V
IH
.
31. Transition is measured
±
500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
32. During this period, the I/O pins are in the output state, and input signals must not be applied.
33. If the CE
or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Switching Waveforms
(continued)
t
AW
t
WC
t
PWE
t
HD
t
SD
t
HA
CE
R/W
OE
DATA OUT
DATA IN
ADDRESS
t
HZOE
t
SA
t
HZWE
t
LZWE
Write Cycle No. 1: R/W Controlled Timing
[25, 26, 27, 28]
[31]
[31]
[28]
[29,30]
NOTE 32
NOTE 32
t
AW
t
WC
t
SCE
t
HD
t
SD
t
HA
CE
R/W
DATA IN
ADDRESS
t
SA
Write Cycle No. 2: CE Controlled Timing
[25, 26, 27, 33]
[29,30]
