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8523CGLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
DATA SHEET
Low Skew, 1-to-4, Differential-to-HSTL
Fanout Buffer
8523
8523 Rev E 6/15/15 1 ©2015 Integrated Device Technology, Inc.
General Description
The 8523 is a low skew, high performance 1-to-4
Differential-to-HSTL Fanout Buffer. The 8523 has two selectable
clock inputs. The CLK, nCLK pair can accept most standard
differential input levels. The PCLK, nPCLK pair can accept LVPECL,
CML, or SSTL input levels. The clock enable is internally
synchronized to eliminate runt pulses on the outputs during
asynchronous assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the
8523 ideal for those applications demanding well defined
performance and repeatability.
Features
• Four differential output HSTL compatible outputs
• Selectable differential CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVDS, HSTL, HCSL, SSTL
• PCLK, nPCLK pair can accept the following differential input
levels: LVPECL, CML, SSTL
• Maximum output frequency: 650MHz
• Translates any single-ended input signal to HSTL levels with
resistor bias on nCLK input
• Additive phase jitter, RMS: 0.082ps (typical), 100MHz f
OUT
• Additive phase jitter, RMS: 0.190ps (typical), 120MHz f
OUT
• Output skew: 30ps (maximum)
• Part-to-part skew: 200ps (maximum)
• 3.3V core, 1.8V output operating supply
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Pin Assignment
Block Diagram
CLK
nCLK
PCLK
nPCLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
CLK_EN
CLK_SEL
D
Q
LE
0
Pullup
Pullup
Pullup
Pulldown
Pulldown
Pulldown
1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
nc
nc
nPCLK
PCLK
nCLK
CLK
CLK_SEL
CLK_EN
GND
V
DD
Q0
nQ0
V
DDO
Q1
nQ1
Q2
nQ2
V
DDO
Q3
nQ3
8523
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm package body
G Package
Top View
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER 2 Rev E 6/15/15
8523 DATA SHEET
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1 GND Power Power supply ground.
2 CLK_EN Input Pullup
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
When LOW, Qx outputs are forced low, nQx outputs are forced high.
LVCMOS / LVTTL interface levels.
3 CLK_SEL Input Pulldown
Clock select input. When HIGH, selects differential PCLK, nPCLK inputs. When
LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels.
4 CLK Input Pulldown Non-inverting differential clock input.
5 nCLK Input Pullup Inverting differential clock input.
6 PCLK Input Pulldown Non-inverting differential LVPECL clock input.
7 nPCLK Input Pullup Inverting differential LVPECL clock input.
8, 9 nc Unused No connect.
10 V
DD
Power Positive supply pin.
11, 12 nQ3, Q3 Output Differential output pair. HSTL interface levels.
13, 18 V
DDO
Power Output supply pins.
14, 15 nQ2, Q2 Output Differential output pair. HSTL interface levels.
16, 17 nQ1, Q1 Output Differential output pair. HSTL interface levels.
19, 20 nQ0, Q0 Output Differential output pair. HSTL interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
Rev E 6/15/15 3 LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
8523 DATA SHEET
Function Tables
Table 3A. Control Input Function Table
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described in Table 3B.
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs Outputs
CLK_EN CLK_SEL Selected Source Q[0:3] nQ[0:3]
0 0 CLK, nCLK Disabled; LOW Disabled; HIGH
0 1 PCLK, nPCLK Disabled; LOW Disabled; HIGH
1 0 CLK, nCLK Enabled Enabled
1 1 PCLK, nPCLK Enabled Enabled
Inputs Outputs
Input to Output Mode PolarityCLK or PCLK nCLK or nPCLK Q[0:3] nQ[0:3]
0 0 LOW HIGH Differential to Differential Non-Inverting
1 1 HIGH LOW Differential to Differential Non-Inverting
0 Biased; NOTE 1 LOW HIGH Single-Ended to Differential Non-Inverting
1 Biased; NOTE 1 HIGH LOW Single-Ended to Differential Non-Inverting
Biased; NOTE 1 0 HIGH LOW Single-Ended to Differential Inverting
Biased; NOTE 1 1 LOW HIGH Single-Ended to Differential Inverting
Enabled
Disabled
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ[0:3]
Q[0:3]
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

8523CGLF

Mfr. #:
Buy 8523CGLF
Manufacturer:
IDT
Description:
Clock Drivers & Distribution Low Skew,1-to-4 Differential-to-HSTL
Lifecycle:
New from this manufacturer.
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