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8523CGLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER 10 Rev E 6/15/15
8523 DATA SHEET
3.3V LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both signals must meet the V
PP
and V
CMR
input
requirements. Figures 4A to 4E show interface examples for the
PCLK/ nPCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
Figure 4A. PCLK/nPCLK Input Driven by a CML Driver
Figure 4C. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
Figure 4E. PCLK/nPCLK Input Driven by an SSTL Driver
Figure 4B. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
Figure 4D. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
P
C
L
K
nP
C
L
K
LVPE
C
L
In
p
u
t
C
M
L
3
.
3V
3
.
3V
3
.
3
V
R3
125Ω
R4
125Ω
R1
84Ω
R2
84Ω
3.3V
o= 50Ω
o= 50Ω
PCLK
nPCLK
3.3V
3.3V
LVPECL
LVPECL
Input
P
C
L
K
nP
C
L
K
LVPE
C
L
In
p
u
t
SS
T
L
2.
5V
2.
5V
3
.
3V
PCLK
nPCLK
3.3V
LVPECL
Input
3.3V
o=50Ω
o=50Ω
R1
100Ω
CML Built-In Pullup
Rev E 6/15/15 11 LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
8523 DATA SHEET
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A1k resistor can be used.
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to ground.
PCLK/nPCLK Inputs
For applications not requiring the use of a differential input, both the
PCLK and nPCLK pins can be left floating. Though not required, but
for additional protection, a 1k resistor can be tied from PCLK to
ground.
Outputs:
HSTL Outputs
All unused LVHSTL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
HSTL Output Termination
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER 12 Rev E 6/15/15
8523 DATA SHEET
Schematic Example
Figure 5 shows a schematic example of the 8523. In this example, the
input is driven by an IDT HSTL driver. The decoupling capacitors
should be physically located near the power pin. For 8523, the
unused clock outputs can be left floating.
Figure 5. 8523 HSTL Buffer Schematic Example
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

8523CGLF

Mfr. #:
Buy 8523CGLF
Manufacturer:
IDT
Description:
Clock Drivers & Distribution Low Skew,1-to-4 Differential-to-HSTL
Lifecycle:
New from this manufacturer.
Delivery:
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