ICS8714008I DATA SHEET FEMTOCLOCK
®
ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESS
TM
AND ETHERNET
ICS8714008DKI REVISION A NOVEMBER 25, 2013 17 ©2013 Integrated Device Technology, Inc.
Applications Information
Overview
The is a high performance FemtoClock Zero Delay Buffer/
Multiplier/Divider which uses external feedback for accurate clock
regeneration and low static and dynamic phase offset. It can be used
in a number different ways:
• Backplane clock multiplier. Many backplane clocks are relatively
low frequency because of heavy electrical loading. The
ICS8714008I can multiply a low frequency backplane clock (e.g.
25MHz) to an appropriate reference clock frequency for PCIe,
Ethernet, 10G Ethernet: 100MHz, 125MHz, 156.25MHz. The
device can also accept a high frequency local reference
(100MHz or 125MHz, for example) and divide the frequency
down to 25MHz M-LVDS to drive a backplane.
• PCIe frequency translator for PCIe add-in cards. In personal
computers, the PCIe reference clock is 100MHz, but some 2.5G
serdes used in PCI Express require a 125MHz reference. The
ICS8714008I can perform the 100MHz 125MHz and
125MHz 100MHz frequency translation for a PCI Express
add-in card while delivering low dynamic and static phase
offset.
• General purpose, low phase noise Zero Delay Buffer
Configuration Notes and Examples
When configuring the output frequency, the main consideration is
keeping the VCO within its range of 490MHz - 660MHz. The designer
must ensure that the VCO will always be within its allowed range for
the expected input frequency range by using the appropriate choice
of feedback output and input dividers. There are two input modes for
the device. In the first mode, a reference clock is provided to the CLK,
nCLK frequency input and this reference clock is divided by the value
of the PDIV divider (selectable ÷1, ÷4, ÷5, ÷8). In the second mode,
a reference clock is provided to the MLVDS, nMLVDS
input pair.
OE_MLVDS determines the input mode. When OE_MLVDS = HIGH
(default), the M-LVDS driver is active and provides an M-LVDS output
to the MLVDS, nMLVDS pins and also the reference to the phase
detector via the PDIV divider. When OE_MLVDS is LOW, the internal
M-LVDS driver is in a High-impedance state and the MLVDS,
nMLVDS pin pair becomes an input and the reference clock applied
to this input is applied to the phase detector.
MLVDS, nMLVDS Output Mode
OE_MLVDS = HIGH (default)
VCO frequency =
CLK, nCLK frequency * FBI_DIV * FBO_DIV/ (PDIV value)
Allowed VCO frequency = 490MHz - 660MHz
Output frequency = VCO frequency/QDIVx value =
CLK, nCLK freq. * FBI_DIV * FBO_DIV/(PDIV*QDIVx)
Example: a frequency synthesizer provides a 125MHz reference
clock to CLK, nCLK frequency
input. The ICS8714008I must provide
a 25MHz M-LVDS clock to the backplane and also provide two local
clocks: one 100MHz HCSL output to an ASIC and one 125MHz
output to the PCI Express serdes.
Solution: Since only two outputs are needed, the two unused outputs
can be disabled. Set OE[2:0] = 001b so that only Q0, nQ0 and Q1,
nQ1 are switching. Since a 25MHz backplane clock is needed from a
125MHz reference clock, set PDIV = ÷5 and OE_MLVDS = HIGH to
enable the M-LVDS driver. 25MHz is applied to the MLVDS, nMLVDS
pins and to the phase detector input. Set FBO_DIV = 4 and FBI_DIV
= 5 which makes the VCO run at 500MHz (25MHz * 4 * 5 = 500MHz).
Set QDIV0 = 0 (÷4) for 125MHz output and QDIV1 = 1 (÷5) for
100MHz output. To figure out what pins must pulled up or down
externally with resistors, check the internal pullup or pulldown
resistors on each pin in the pin description table or on the block
diagram. PDIV[1:0] defaults to 00/÷4 and we need 01/÷5. So PDIV1
can be left floating (it has an internal pulldown resistor) and PDIV0
must be driven or pulled up via external pullup resistor to HIGH state.
OE_MLVDS defaults to Logic 1 (active) and this is what we need, so
that pin can be left floating. The FBO_DIV and FBIN dividers default
to the desired values, so their respective control pins can be left
floating (FBO_DIV and FBI_DIV[1:0]). QDIV0 needs to be ÷4, which
is a default value so this pin can be left floating. QDIV1 must be HIGH
for ÷5, so this pin must be pulled high or driven high externally.
OE[2:0] = 001, so OE0 can Float and OE[2:1] must be pulled Low.
MLVDS, nMLVDS Input Mode
OE_MLVDS = LOW
VCO frequency = MLVDS, nMLVDS freq. * FBI_DIV * FBO_DIV
Output frequency = VCO frequency/QDIVx value = MLVDS,
nMLVDS freq. * FBI_DIV * FBO_DIV/(QDIVx)
Example - backplane: The 8714008I sits on a backplane card and
must multiply a 25MHz reference that comes from the backplane into
one 125MHz reference clock for a Gigabit Ethernet serdes and one
100MHz reference clock for a PCI Express serdes.
Solution. Since only two outputs are needed, the two unused outputs
can be disabled. Set OE[2:0] = 001b so that only Q0, nQ0 and Q1,
nQ1 are switching. Set OE_MLVDS = 0 so the internal M-LVDS driver
is in a High-impedance state, allowing the MLVDS, nMLVDS
pins to
function as an input for the 25MHz clock reference. Set FBO_DIV =
4 and FBI_DIV = 5 which makes the VCO run at 500MHz (25MHz *
4 * 5 = 500MHz). Set QDIV0 = 0 (÷4) for 125MHz output and QDIV1
= 1 (÷5) for 100MHz output. To figure out what pins must pulled up or
down externally with resistors, check the internal pullup or pulldown
resistors on each pin in the pin description table or on the block
diagram. PDIV[1:0] defaults to 00/÷4 and we need 01/÷5. So PDIV1
can be left floating (it has an internal pulldown resistor) and PDIV0
must be driven or pulled up via external pullup resistor to HIGH state.
OE_MLVDS defaults to Logic 1(active) and this is what we need, so
that pin can be left floating. The FBO_DIV and FBIN dividers default
to the desired values, so their respective control pins can be left
floating (FBO_DIV and FBI_DIV[1:0]). QDIV0 needs to be ÷4, which
is a default value so this pin can be left floating. QDIV1 must be HIGH
for ÷5, so this pin must be pulled high or driven high externally.
