SST39VF1682-70-4I-B3KE-T

duce a ‘0’. Once the internal Erase operation is completed, DQ

after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase,

the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling tim-

ing diagram and Figure 21 for a flowchart.

During the internal Program or Erase operation, any consecutive attempts to read DQ

alternating “1”s and “0”s, i.e., toggling between 1 and 0. When the internal Program or Erase operation

is completed, the DQ

, Block-, or Chip-Erase, the toggle bit (DQ

An additional Toggle Bit is available on DQ

Write operation. See Figure 8 for Toggle Bit timing diagram and Figure 21 for a flowchart.

writes.

Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.

V

Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre-

vents inadvertent writes during power-up or power-down.

The SST39VF1682 supports top hardware block protection, which protects the top 64 KByte block of

the device. The SST39VF1681 supports bottom hardware block protection, which protects the bottom

64 KByte block of the device. The Boot Block address ranges are described in Table 3. Program and

Erase operations are prevented on the 64 KByte when WP# is low. If WP# is left floating, it is internally

held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase opera-

tions on that block.

The RST# pin provides a hardware method of resetting the device to read array data. When the RST#

pin is held low for at least T

no internal Program/Erase operation is in progress, a minimum period of T

byte sequence. The three-byte load sequence is used to initiate the Program operation, providing opti-

mal protection from inadvertent Write operations, e.g., during the system power-up or power-down.

Any Erase operation requires the inclusion of six-byte sequence. These devices are shipped with the

Software Data Protection permanently enabled. See Table 6 for the specific software command codes.

During SDP command sequence, invalid commands will abort the device to Read mode within T

The Product Identification mode identifies the devices as the SST39VF1681 and SST39VF1682, and manu-

facturer as SST. Users may use the software Product Identification operation to identify the part (i.e., using

the device ID) when using multiple manufacturers in the same socket. For details, see Table 6 for software

operation, Figure 12 for the software ID Entry and Read timing diagram, and Figure 22 for the software ID

Entry command sequence flowchart.

rectly. Please note that the software ID Exit/CFI Exit command is ignored during an internal Program or

To program the user segment of the Security ID, the user must use the Security ID Byte-Program com-

mand. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once this

is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables any

future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither Sec

The Security ID space can be queried by executing a three-byte command sequence with Enter-Sec-