8-O/P 1.8V PCIE GEN 1-2-3 CLOCK GENERATOR W/ZO=100OHMS 10 OCTOBER 18, 2016
9FGV0841 DATASHEET
General SMBus Serial Interface Information
How to Write
Controller (host) sends a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) sends the byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte
N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
Note: SMBus address is latched on SADR pin.
How to Read
Controller (host) will send a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N+X-1
IDT clock sends Byte 0 through Byte X (if X
(H)
was
written to Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ACK
O
OO
OO
O
Byte N + X - 1
ACK
PstoP bit
Index Block Read Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address
RD ReaD
ACK
Data Byte Count=X
ACK
X Byte
Beginning Byte N
ACK
O
OO
OO
O
Byte N + X - 1
N Not acknowledge
PstoP bit
OCTOBER 18, 2016 11 8-O/P 1.8V PCIE GEN 1-2-3 CLOCK GENERATOR W/ZO=100OHMS
9FGV0841 DATASHEET
SMBus Table: Output Enable Register
1
Byte 0 Name Control Function Type 0 1 Default
Bit 7
DIF OE7 Output Enable RW Low/Low Enabled 1
Bit 6
DIF OE6 Output Enable RW Low/Low Enabled 1
Bit 5
DIF OE5 Output Enable RW Low/Low Enabled 1
Bit 4
DIF OE4 Output Enable RW Low/Low Enabled 1
Bit 3
DIF OE3 Output Enable RW Low/Low Enabled 1
Bit 2
DIF OE2 Output Enable RW Low/Low Enabled 1
Bit 1
DIF OE1 Output Enable RW Low/Low Enabled 1
Bit 0
DIF OE0 Output Enable RW Low/Low Enabled 1
1. A low on these bits will overide the OE# pin and force the differential output Low/Low
SMBus Table: SS Readback and Control Register
Byte 1 Name Control Function Type 0 1 Default
Bit 7
SSENRB1 SS Enable Readback Bit1
R
Latch
Bit 6
SSENRB1 SS Enable Readback Bit0
R
Latch
Bit 5
SSEN_SWCNTRL Enable SW control of SS RW
Values in B1[7:6]
control SS amount
Values in B1[4:3]
control SS amount.
0
Bit 4
SSENSW1 SS Enable Software Ctl Bit1
RW
1
0
Bit 3
SSENSW0 SS Enable Software Ctl Bit0
RW
1
0
Bit 2
1
Bit 1
AMPLITUDE 1 RW 00 = 0.6V 01 = 0.7V 1
Bit 0
AMPLITUDE 0 RW 10= 0.8V 11 = 0.9V 0
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
SMBus Table: DIF Slew Rate Control Register
Byte 2 Name Control Function Type 0 1 Default
Bit 7
SLEWRATESEL DIF7 Adjust Slew Rate of DIF7 RW Slow Setting Fast Setting 1
Bit 6
SLEWRATESEL DIF6 Adjust Slew Rate of DIF6 RW Slow Setting Fast Setting 1
Bit 5
SLEWRATESEL DIF5 Adjust Slew Rate of DIF5 RW Slow Setting Fast Setting 1
Bit 4
SLEWRATESEL DIF4 Adjust Slew Rate of DIF4 RW Slow Setting Fast Setting 1
Bit 3
SLEWRATESEL DIF3 Adjust Slew Rate of DIF3 RW Slow Setting Fast Setting 1
Bit 2
SLEWRATESEL DIF2 Adjust Slew Rate of DIF2 RW Slow Setting Fast Setting 1
Bit 1
SLEWRATESEL DIF1 Adjust Slew Rate of DIF1 RW Slow Setting Fast Setting 1
Bit 0
SLEWRATESEL DIF0 Adjust Slew Rate of DIF0 RW Slow Setting Fast Setting 1
SMBus Table: Nominal Vhigh Amplitude Control/ REF Control Register
Byte 3 Name Control Function Type 0 1 Default
Bit 7
RW 00 = 0.9V/ns 01 =1.3V/ns 0
Bit 6
RW 10 = 1.6V/ns 11 = 1.8V/ns 1
Bit 5
REF Power Down Function Wake-on-Lan Enable for REF RW
REF does not run in
Power Down
REF runs in Power
Down
0
Bit 4
REF OE REF Output Enable RW Low Enabled 1
Bit 3
1
Bit 2
1
Bit 1
1
Bit 0
1
Byte 4 is Reserved
00' for SS_EN_tri = 0, '01' for SS_EN_tri
= 'M', '11 for SS_EN_tri = '1'
00' = SS Off, '01' = -0.25% SS,
'10' = Reserved, '11'= -0.5% SS
Reserved
Controls Output Amplitude
Reserved
Reserved
Reserved
REF Slew Rate Control
Reserved
8-O/P 1.8V PCIE GEN 1-2-3 CLOCK GENERATOR W/ZO=100OHMS 12 OCTOBER 18, 2016
9FGV0841 DATASHEET
Recommended Crystal Characteristics (3225 package)
SMBus Table: Revision and Vendor ID Register
Byte 5 Name Control Function Type 0 1 Default
Bit 7
RID3
R
0
Bit 6
RID2
R
0
Bit 5
RID1
R
0
Bit 4
RID0
R
0
Bit 3
VID3
R
0
Bit 2
VID2
R
0
Bit 1
VID1
R
0
Bit 0
VID0
R
1
SMBus Table: Device Type/Device ID
Byte 6 Name Control Function Type 0 1 Default
Bit 7
Device Type1
R
0
Bit 6
Device Type0
R
0
Bit 5
Device ID5
R
0
Bit 4
Device ID4
R
0
Bit 3
Device ID3
R
1
Bit 2
Device ID2
R
0
Bit 1
Device ID1
R
0
Bit 0
Device ID0
R
0
SMBus Table: Byte Count Register
Byte 7 Name Control Function Type 0 1 Default
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
BC4 RW 0
Bit 3
BC3 RW 1
Bit 2
BC2 RW 0
Bit 1
BC1 RW 0
Bit 0
BC0 RW 0
001000 binary or 08 hexDevice ID
Reserved
00 = FGx, 01 = DBx ZDB/FOB,
10 = DMx, 11= DBx FOB
Device Type
Reserved
A rev = 0000Revision ID
Writing to this register will configure how
many bytes will be read back, default is
= 8 bytes.
Byte Count Programming
Reserved
0001 = IDTVENDOR ID
PARAMETER VALUE UNITS NOTES
Frequency 25 MHz 1
Resonance Mode Fundamental
-
1
Frequency Tolerance @ 25°C
±
20 PPM Max 1
Frequency Stability, ref @ 25°C Over
Operating Temperature Range
±
20 PPM Max 1
Temperature Range (commerical) 0~70 °
C
1
Temperature Range (industrial) -40~85 °
C
2
Equivalent Series Resistance (ESR) 50
Max 1
Shunt Capacitance (C
O
)7pF Max1
Load Capacitance (C
L
)8pF Max1
Drive Level 0.3 mW Max 1
Aging per year
±5
PPM Max 1
Notes:
1. FOX 603-25-150.
2. For I-temp, FOX 603-25-261.

9FGV0841AKLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products PCIe CLOCK GENERATOR GEN 1/2/3, 8 OUT
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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