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9FGV0841AKLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
OCTOBER 18, 2016 7 8-O/P 1.8V PCIE GEN 1-2-3 CLOCK GENERATOR W/ZO=100OHMS
9FGV0841 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Supply Voltage VDDxx
Supply voltage for core, analog and single-ended
LVCMOS outputs
1.7 1.8 1.9 V
Output Supply Voltage VDDIO Supply voltage for differential Low Power Outputs 0.9975 1.05-1.8 1.9 V
Commmercial range 0 25 70 °C
Industrial range -40 25 85 °C
Input High Voltage V
IH
Single-ended inputs, except SMBus 0.75 V
DD
V
DD
+ 0.3 V
Input Mid Voltage V
IM
Single-ended tri-level inputs ('_tri' suffix) 0.4 V
DD
0.5 V
DD
0.6 V
DD
V
Input Low Voltage V
IL
Single-ended inputs, except SMBus -0.3 0.25 V
DD
V
Output High Voltage V
IH
Single-ended outputs, except SMBus. I
OH
= -2mA V
DD
-0.45 V
Output Low Voltage V
IL
Single-ended outputs, except SMBus. I
OL
= -2mA 0.45 V
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 uA
I
INP
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
-200 200 uA
Input Frequency F
in
XTAL, or X1 input 23 25 27 MHz
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
OU
T
Output pin capacitance 6 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
0.6 1.8 ms 1,2
SS Modulation Frequency f
MOD
Allowable Frequency
(Triangular Modulation)
30 31.6 33 kHz 1
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
1 3 3 clocks 1,3
Tdrive_PD# t
DRVPD
DIF output enable after
PD# de-assertion
20 300 us 1,3
Tfall t
F
Fall time of single-ended control inputs 5 ns 2
Trise t
R
Rise time of single-ended control inputs 5 ns 2
SMBus Input Low Voltage V
ILSMB
V
DDSMB
= 3.3V, see note 4 for V
DDSMB
< 3.3V 0.6 V
SMBus Input High Voltage V
IHSMB
V
DDSMB
= 3.3V, see note 5 for V
DDSMB
< 3.3V 2.1 3.6 V 4
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.4 V
SMBus Sink Current I
PULLUP
@ V
OL
4mA
Nominal Bus Voltage V
DDSMB
1.7 3.6 V
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency
f
MAXSMB
Maximum SMBus operating frequency 400 kHz 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
Input Current
Ambient Operating
Temperature
T
AMB
Capacitance
3
Time from deassertion until out
p
uts are >200 mV
4
For V
DDSMB
< 3.3V, V
IHSMB
>= 0.65xV
DDSMB
8-O/P 1.8V PCIE GEN 1-2-3 CLOCK GENERATOR W/ZO=100OHMS 8 OCTOBER 18, 2016
9FGV0841 DATASHEET
Electrical Characteristics–DIF Low Power HCSL Outputs
Electrical Characteristics–Differential Output Phase Jitter Parameters
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Scope avera
g
in
g
on fast settin
g
1.6 2.3 3.5
V/ns
1,2,3
Scope averaging on slow setting 1.3 1.9 2.9
V/ns
1,2,3
Slew rate matchin
g
Δ
Trf Slew rate matchin
g
, Scope avera
g
in
g
on 7 20
%
1,2,4
Voltage High V
HIGH
660 784 850 7
Voltage Low V
LOW
-150 -33 150 7
Max Voltage Vmax 816 1150 7
Min Volta
g
e Vmin -300 -42 7
Vswin
g
Vswin
g
Scope avera
g
in
g
off 300 1634 mV 1,2,7
Crossing Voltage (abs) Vcross_abs Scope averaging off 250 427 550 mV 1,5,7
Crossing Voltage (var)
Δ
-Vcross Scope averaging off 12 140 mV 1,6,7
2
Measured from differential waveform
7
At default SMBus amplitude settin
g
s.
Measurement on single ended signal using
absolute value. (Scope avera
g
in
g
off)
mV
Slew rate Trf
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
mV
1
Guaranteed by design and characterization, not 100% tested in production.
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting
Δ
-Vcross to be smaller than Vcross absolute.
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX
IND.
LIMIT
UNITS Notes
t
jp
hPCIeG1
PCIe Gen 1 25 35 86 ps (p-p) 1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.9 1.2 3
ps
(rms)
1,2,3
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
1.6 2.1
3.1
ps
(rms)
1,2,3
t
jphPCIeG3
PCIe Gen 3 Common Clock Architecture
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
0.4 0.5
1
ps
(rms)
1,2,3
t
jphPCIeG3SRn
S
PCIe Gen 3 Separate Reference No Spread (SRnS)
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
0.4 0.5
0.7
ps
(rms)
1,2,3
1
Guaranteed by design and characterization, not 100% tested in production.
4
Applies to all differential outputs
Phase Jitter, PLL Mode
4
t
jphPCIeG2
2
See http://www.pcisig.com for complete specs
3
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
OCTOBER 18, 2016 9 8-O/P 1.8V PCIE GEN 1-2-3 CLOCK GENERATOR W/ZO=100OHMS
9FGV0841 DATASHEET
Electrical Characteristics–REF
Clock Periods–Differential Outputs with Spread Spectrum Disabled
Clock Periods–Differential Outputs with Spread Spectrum Enabled
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBO
L
CONDITIONS MIN TYP MAX UNITS Notes
Long Accuracy ppm see Tperiod min-max values ppm 1,2
Clock period T
p
eriod
25 MHz output 40 ns 2
Rise/Fall Slew Rate t
rf1
Byte 3 = 1F, 20% to 80% of VDDREF 0.6 1 1.6 V/ns 1
Rise/Fall Slew Rate t
rf1
Byte 3 = 5F, 20% to 80% of VDDREF 0.9 1.4 2.2 V/ns 1,3
Rise/Fall Slew Rate t
rf1
Byte 3 = 9F, 20% to 80% of VDDREF 1.1 1.7 2.7 V/ns 1
Rise/Fall Slew Rate t
rf1
Byte 3 = DF, 20% to 80% of VDDREF 1.1 1.8 2.9 V/ns 1
Duty Cycle d
t1X
V
T
= VDD/2 V 45 49.1 55 % 1,4
Duty Cycle Distortion d
tcd
V
T
= VDD/2 V 0 2 4 % 1,5
Jitter, cycle to cycle t
j
c
y
c-c
y
c
V
T
= VDD/2 V 19.1 250 ps 1,4
Noise floor t
j
dBc1k
1kHz offset -129.8 -105 dBc 1,4
Noise floor t
j
dBc10k
10kHz offset to Nyquist -143.6 -115 dBc 1,4
Jitter, phase t
jphREF
12kHz to 5MHz 0.63 1.5
ps
(rms)
1,4
1
Guaranteed by design and characterization, not 100% tested in production.
3
Default SMBus Value
4
When driven by a crystal.
5
When driven by an external oscillator via the X1 pin, X2 should be floating.
2
All Lon
g
Term Accuracy and Clock Period specifications are
g
uaranteed assumin
g
that REF is trimmed to 25.00 MHz
0
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Ma
x
+SSC
Short-Term
Average
Ma
x
+c2c jitter
AbsPer
Max
DIF 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2
Measurement Window
UnitsSSC OFF
Center
Freq.
MHz
Notes
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Ma
x
+SSC
Short-Term
Average
Ma
x
+c2c jitter
AbsPer
Max
DIF 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2
1
Guaranteed by desi
g
n and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz
Measurement Window
UnitsSSC ON
Center
Freq.
MHz
Notes
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

9FGV0841AKLF

Mfr. #:
Buy 9FGV0841AKLF
Manufacturer:
IDT
Description:
Clock Generators & Support Products PCIe CLOCK GENERATOR GEN 1/2/3, 8 OUT
Lifecycle:
New from this manufacturer.
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