LTC4308
8
4308f
Start-Up
When the LTC4308 fi rst receives power on its V
CC
pin,
either during power-up or live insertion, it starts in an
under voltage lockout (UVLO) state, ignoring any activity
on the SDA or SCL pins until V
CC
rises above 2V (typical).
This ensures the LTC4308 does not try to function until
enough supply voltage is present.
During this time, the 1V precharge circuitry is actively
forcing 1V through 100k nominal resistors to the SDAOUT
and SCLOUT pins. Because SDAOUT and SCLOUT pins
may be plugged into a live backplane, where the voltage
on the backplane SDA and SCL busses can be anywhere
between 0V and V
CC
, precharging SCLOUT and SDAOUT
to 1V minimizes the worst-case voltage differential these
pins will see at the moment of contact, therefore minimizing
the amount of disturbance caused by the I/O card.
Once the LTC4308 exits from UVLO, it monitors both the
input and output pins for either a stop bit or a bus idle
condition to indicate the completion of data transactions.
When both sides are idle or one side has a stop bit while the
other is idle, the connection circuitry is activated, joining
the SDA and SCL pins on the input bus with those on the
output bus. Because SDAIN and SCLIN are monitored for
a stop bit or bus idle as a condition for connection, they
may also be used for Hot-Swapping, but note that these
pins are not precharged.
Connection Circuitry
Once the connection circuitry is activated, the functionality
of the input and output bus of the respective SDA or SCL
pins is identical. A low forced on either output or input pin
at any time results in both pin voltages forced low. The
LTC4308 SCLOUT and SDAOUT busses are tolerant of I
2
C
bus DC logic low voltages up to the V
IL
specifi cation of
0.3 • V
CC
, while the SCLIN and SDAIN busses are tolerant
of bus logic low voltages up to 0.6V. A high occurs when
all devices on the input and output pins release high.
When the LTC4308 senses a rising edge on either of the
output busses, with a slew rate greater than 0.8V/μs, the
internal pull-down device for the respective bus is deacti-
vated at bus voltages as low as 0.48V. This methodology
maximizes the effectiveness of the rise time accelerator
circuitry and maintains compatibility with other devices
in the LTC4300 bus buffer family. Care must be taken to
ensure devices participating in clock stretching or arbitra-
tion is capable of forcing logic low voltages below 0.48V
at the LTC4308’s SCLOUT and SDAOUT pins.
These important features ensure the I
2
C specifi cation
protocols such as clock stretching, clock synchroniza-
tion, arbitration, and acknowledge function seamlessly
in all cases as specifi ed, regardless of how the devices in
the system are connected to the LTC4308.
Another key feature provided by the connection circuitry
is input and output bus capacitance isolation through
bidirectional buffering. Because of this isolation, the
waveforms on the input busses look slightly different than
the corresponding output bus waveforms, as described
in the next two sections.
Offset Voltages
When a logic low is driven on SDAIN or SCLIN, the LTC4308
regulates SDAOUT or SCLOUT, respectively, to a higher
voltage, typically 300mV above the driven low voltage.
When a logic low is driven on SCLOUT or SDAOUT, the
LTC4308 regulates SCLIN or SDAIN, respectively, to a volt-
age that is typically 200mV below the driven low voltage.
These offsets are nearly independent of pull-up current
(see Typical Performance Characteristics).
OPERATION
