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953008BFLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
953008
Datasheet
1076—08/06/09
Pin Configuration
Recommended Application:
VIA PT890/894 style chipset
Output Features:
• 2 - 0.7V current-mode differential CPU pairs
• 10 - PCI, 33MHz
• 2 - REF, 14.318MHz
• 3 - 3V66, 66.66MHz
• 1 - 48MHz
• 1 - 24/48MHz selectable output
• 3 - PCI Express
TM
0.7V current mode differential pairs
• 1 CPU/PCI Express 0.7 current mode selectable
differential pair
Programmable Timing Control Hub™ for Next Gen P4™ processor
Functionality
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• 3V66 outputs cycle-cycle jitter < 250ps
• PCI outputs cycle-cycle jitter < 500ps
• PCI Express outputs cycle-cycle jitter < 125ps
VDDA 1 56 GND
GND 2 55 IREF
VDDREF 3 54 CPUCLKT0
**F S
L
0/REF0 4 53 CPUCLKC0
FS
L
1/REF1 5 52 GNDCPU
X1 6 51 CPUCLKT1
X2 7 50 CPUCLKC1
GNDREF 8 49 VDDCPU
VttPWR_GD/PD# 9 48 SDATA
**FS
L
2/PCICLK0 10 47 CPUCLKT2/PCIEXT0
**FS3/~PCICLK1 11 46 CPUCLKC2/PCIEXC0
PCICLK2 12 45 VDDPCIEX
PCICLK3 13 44 PCIEXT1
GNDPCI 14 43 PCIEXC1
VDDPCI 15 42 PCIEXT2
PCICLK4 16 41 PCIEXC2
PCICLK5 17 40 GNDPCIEX
PCICLK6
18 39 VDDPCIEX
VDDPCI 19 38 PCIEXT3
GNDPCI 20 37 PCIEXC3
PCICLK7
21 36 GNDPCIEX
PCICLK8
22 35 SCLK
PCICLK9
23 34 GND3V66
*Turbo# 24 33 3V66_0
Reset# 25 32 3V66_1/FS4**
VDD48 26 31 3V66_2/Mode0**
48MHz 27 30 VDD3V66
*Sel24_48#/24_48MHz 28 29 GND48
56-Pin SSOP
*These inputs have 120K internal pull-up resistors to VDD.
**These inputs have 120K internal pull-down resistors to GND.
~This output is default 2X drive strength.
ICS953008
Bit4 Bit3 Bit2 Bit1 Bit0 CPU PCIE
X
3v66 PCI
FS4 FS3 FSL2 FSL1 FSL0 MHz MHz MHz MHz
00000
266.66 100.00 66.67 33.33
00001
133.33 100.00 66.67 33.33
00010
200.00 100.00 66.67 33.33
00011
N/A N/A N/A N/A
0 0 1 0 0 N/A N/A N/A N/A
00101
100.00 100.00 66.67 33.33
00110
400.00 100.00 66.67 33.33
00111
200.00 100.00 66.67 33.33
01000
266.66 133.33 66.67 33.33
01001
133.33 133.33 66.67 33.33
01010
200.00 133.33 66.67 33.33
01011
N/A N/A N/A N/A
01100
N/A N/A N/A N/A
01101
100.00 133.33 66.67 33.33
01110
400.00 133.33 66.67 33.33
01111
200.00 133.33 66.67 33.33
1 0 0 0 0 269.33 101.00 67.33 33.67
10001
134.66 101.00 67.33 33.67
10010
202.00 101.00 67.33 33.67
10011
N/A N/A N/A N/A
10100
274.66 103.00 68.66 34.33
10101
137.33 103.00 68.66 34.33
10110
206.00 103.00 68.67 34.33
10111
N/A N/A N/A N/A
11000
279.99 105.00 70.00 35.00
11001
140.00 105.00 70.00 35.00
11010
210.00 105.00 70.00 35.00
11011
N/A N/A N/A N/A
11100
287.99 108.00 72.00 36.00
11101
144.00 108.00 72.00 36.00
11110
216.00 108.00 72.00 36.00
11111
N/A N/A N/A N/A
2
953008
Datasheet
1076—08/06/09
Pin Description
PIN #
PIN NAME TYPE DESCRIPTION
1 VDDA PWR 3.3V power for the PLL core.
2 GND PWR Ground pin.
3 VDDREF PWR Ref, XTAL power supply, nominal 3.3V
4**FSL0/REF0 I/O
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / 14.318 MHz reference
clock.
5FSL1/REF1 I/O
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / 14.318 MHz reference
clock.
6 X1 IN Crystal input, Nominally 14.318MHz.
7 X2 OUT Crystal output, Nominally 14.318MHz
8 GNDREF PWR Ground pin for the REF outputs.
9 VttPWR_GD/PD# IN
This 3.3V LVTTL input is a level sensitive strobe used to determine when
latch inputs are valid and are ready to be sampled. This is an active high
input. / Asynchronous active low input pin used to power down the device
into a low power state.
10 **FSL2/PCICLK0 I/O
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / 3.3V PCI clock output.
11 **FS3/PCICLK1 I/O Frequency select latch input pin / 3.3V PCI clock output.
12 PCICLK2 OUT PCI clock output.
13 PCICLK3 OUT PCI clock output.
14 GNDPCI PWR Ground pin for the PCI outputs
15 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V
16 PCICLK4 OUT PCI clock output.
17 PCICLK5 OUT PCI clock output.
18 PCICLK6 OUT PCI clock output.
19 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V
20 GNDPCI PWR Ground pin for the PCI outputs
21 PCICLK7 OUT PCI clock output.
22 PCICLK8 OUT PCI clock output.
23 PCICLK9 OUT PCI clock output.
24 *Turbo# IN
Real time input pin to change frequency to a pre-programmed under or over
clock entries located in the Rom table.
25 Reset# OUT
Real time system reset signal for frequency gear ratio change or watchdog
timer timeout. This signal is active low.
26 VDD48 PWR Power pin for the 48MHz output.3.3V
27 48MHz OUT 48MHz clock output.
28 *Sel24_48#/24_48MHz I/O
Latched select input for 24/48MHz output / 24/48MHz clock output.
1=24MHz, 0 = 48MHz.
3
953008
Datasheet
1076—08/06/09
Pin Description
PIN #
PIN NAME TYPE DESCRIPTION
29 GND48 PWR Ground pin for the 48MHz outputs
30 VDD3V66 PWR Power pin for the 3.3V 66MHz clocks.
31 3V66_2/Mode0** I/O
3.3V 66.66MHz clock output / Function select latch input pin for
CPUCLK/PCIEX selectable pin. 0 = PCIEXT/C ; 1 = CPUCLKT/C.
32 3V66_1/FS4** I/O 3.3V 66.66MHz clock output. / Frequency select latch input pin
33 3V66_0 OUT 3.3V 66.66MHz clock output
34 GND3V66 PWR Ground pin for the 3.3V 66MHz clocks
35 SCLK IN Clock pin of SMBus circuitry, 5V tolerant.
36 GNDPCIEX PWR Ground pin for the PCI-EX outputs
37 PCIEXC3 OUT Complement clock of differential PCI_Express pair.
38 PCIEXT3 OUT True clock of differential PCI_Express pair.
39 VDDPCIEX PWR Power supply for PCI Express clocks, nominal 3.3V
40 GNDPCIEX PWR Ground pin for the PCI-EX outputs
41 PCIEXC2 OUT Complement clock of differential PCI_Express pair.
42 PCIEXT2 OUT True clock of differential PCI_Express pair.
43 PCIEXC1 OUT Complement clock of differential PCI_Express pair.
44 PCIEXT1 OUT True clock of differential PCI_Express pair.
45 VDDPCIEX PWR Power supply for PCI Express clocks, nominal 3.3V
46 CPUCLKC2/PCIEXC0 OUT
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias./
Complement clock of differential PCIEX pair
47 CPUCLKT2/PCIEXT0 OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias. / True clock of
differential PCIEX pair
48 SDATA I/O Data pin for SMBus circuitry, 5V tolerant.
49 VDDCPU PWR Supply for CPU clocks, 3.3V nominal
50 CPUCLKC1 OUT
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
51 CPUCLKT1 OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
52 GNDCPU PWR Ground pin for the CPU outputs
53 CPUCLKC0 OUT
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
54 CPUCLKT0 OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
55 IREF OUT
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
56 GND PWR Ground pin.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

953008BFLF

Mfr. #:
Buy 953008BFLF
Manufacturer:
IDT
Description:
Clock Generators & Support Products PC MAIN CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
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