953008BFLF Datasheet 953008BFLF, 953008BFLFT | P7-P9

7

953008

Datasheet

1076—08/06/09

I

2

C Table: Frequency Select Register

Bit 7

FS Source

Frequency H/W IIC

Select

RW 0

Bit 6

SS_EN1 PLL1 Spread Enable RW 0

Bit 5

SS_EN2 PLL2 Spread Enable RW 1

Bit 4

FS4 Freq Select Bit 4 RW Latch

Bit 3

FS3 Freq Select Bit 3 RW Latch

Bit 2

FSL2 Freq Select Bit 2 RW Latch

Bit 1

FSL1 Freq Select Bit 1 RW Latch

Bit 0

FSL0 Freq Select Bit 0 RW Latch

I

2

C Table: General Device Behaviour Register

Bit 7

IREF Bit0

IREF Mulitiplier

Programming Bits

RW 0

Bit 6

SEL24_48MHz Output Select RW Latch

Bit 5

Mode 0 Output Select RW Latch

Bit 4

PCIEX PLL Cntrl PCIEX PLL Source RW 0

Bit 3

3V66/PCI PLL Cntrl

3V66/PCI PLL

Source

RW 0

Bit 2

ASYNC1

RW 0

Bit 1

ASYNC0

RW 0

Bit 0

Reserved Reserved RW 0

I

2

C Table: Output Control Register

Bit 7

REF0 Output Control RW 1

Bit 6

REF1 Output Control RW 1

Bit 5

PCICLK0 Output Control RW 1

Bit 4

PCICLK1 Output Control RW 1

Bit 3

PCICLK2 Output Control RW 1

Bit 2

PCICLK3 Output Control RW 1

Bit 1

PCICLK4 Output Control RW 1

Bit 0

PCICLK5 Output Control RW 1

I

2

C Table: Output Control Register

Bit 7

48MHz Output Control RW 1

Bit 6

24_48MHz Output Control RW 1

Bit 5

3V66_2 Output Control RW 1

Bit 4

3V66_1 Output Control RW 1

Bit 3

3V66_0 Output Control RW 1

Bit 2

PCICLK6 Output Control RW 1

Bit 1

PCICLK7 Output Control RW 1

Bit 0

PCICLK8 Output Control RW 1

Control Function Type

-

3V66/PCI Async

Freq Prog bits

-

PWD

-

Name Control Function Type 0

7 x Iref6 x Iref

48MHz

Disable

0

Name Type

PWD

1

01

Latch Inputs

OFF

Enable

-

PWD

-

Byte 1 Pin #

-

Byte 3

-

Name

-

Pin #

-

Name

-

Byte 2 Pin #

-

TypeByte 0 Pin #

-

Control Function

OFF

IIC

ON

See Table1:PLL1 Frequency Selection

Table

Sync

--

00 = PLL2 10 = 75.4/37.7

01 = 66.0/33.0

24MHz

11 = 88.0/44.0

Async

01

Enable

Disable

Disable Enable

Enable

EnableDisable

Disable

Enable

Disable Enable

Disable

1

Disable

Enable

Disable

Disable Enable

PCIEXCLKT/C0 CPUCLKT/C2

Enable

Disable Enable

Sync Async (PLL2)

Enable

8

953008

Datasheet

1076—08/06/09

I

2

C Table: Out

p

ut Control Re

g

ister

Bit 7

PCIEXCLKT/C3 Output Control RW 1

Bit 6

PCIEXCLKT/C2 Output Control RW 1

Bit 5

PCIEXCLKT/C1 Output Control RW 1

Bit 4

CPUCLK2/PCIEX0 Output Control RW 1

Bit 3

CPUCLKT/C1 Output Control RW 1

Bit 2

CPUCLKT/C0 Output Control RW 1

Bit 1

PCICLK9 Output Control RW 1

Bit 0

Reserved Reserved RW 1

I

2

C Table: Programmable Skew Control Register

Bit 7

PCISkw3 RW 0000:0 0100:150 1000:300 1100:450 1

Bit 6

PCISkw2 RW 0001:N/A 0101:N/A 1001:N/A 1101:600 1

Bit 5

PCISkw1 RW 0010:N/A 0110:N/A 1010:N/A 1110:750 0

Bit 4

PCISkw0 RW 0011:N/A 0111:N/A 1011:N/A 1111:900 0

Bit 3

3V66Skw3 RW 0000:0 0100:150 1000:300 1100:450 1

Bit 2

3V66Skw2 RW 0001:N/A 0101:N/A 1001:N/A 1101:600 0

Bit 1

3V66Skw1 RW 0010:N/A 0110:N/A 1010:N/A 1110:750 0

Bit 0

3V66Skw0 RW 0011:N/A 0111:N/A 1011:N/A 1111:900 0

I

2

C Table: Reserved Register

Bit 7

Reserved

RW 1

Bit 6

Reserved

RW 1

Bit 5

Reserved

RW 1

Bit 4

Reserved

RW 1

Bit 3

Reserved

RW 0

Bit 2

Reserved

RW 1

Bit 1

Reserved

RW 1

Bit 0

Reserved

RW 1

I

2

C Table: Vendor ID Register

Bit 7

REVID3 Revision ID R 0

Bit 6

REVID2 Revision ID R 0

Bit 5

REVID1 Revision ID R 0

Bit 4

REVID0 Revision ID R 0

Bit 3

VID3 Vendor ID R 0

Bit 2

VID2 Vendor ID R 0

Bit 1

VID1 Vendor ID R 0

Bit 0

VID0 Vendor ID R 1

-

--

-

001 = ICS

--

-

Type

-

Control Function

Disable

0

Disable

-

Byte 6 Pin #

Control Function

Reserved

-

Reserved

Disable

0

-

Pin #

Name

-

Byte 4

-

Pin #

Name

Type

Type 0 1

1

01

Type

-

PWD

-

Pin #

-

Byte 7

-

Byte 5

Control Function

CPU-PCI 7 Steps

Skew Control (ps)

Control Function

Enable

1

Disable Enable

Enable

--

-

Enable

--

CPU-3V66 7 Steps

Skew Control (ps)

9

953008

Datasheet

1076—08/06/09

I

2

C Table: Byte Count Register

Bit 7

BC7 RW 0

Bit 6

BC6 RW 0

Bit 5

BC5 RW 0

Bit 4

BC4 RW 0

Bit 3

BC3 RW 1

Bit 2

BC2 RW 1

Bit 1

BC1 RW 1

Bit 0

BC0 RW 1

I

2

C Table: WD Time Control Register

Bit 7

WDEN

Watchdog Alarm

Enable (Hard alarm

only)

RW 0

Bit 6

WDSEN

Watchdog Soft

Alarm Enable (Hard

and Soft alarm)

RW 0

Bit 5

WD Hard Status

WD Hard Alar m

Status

Rx

Bit 4

WD Soft Status

WD Soft Alarm

Status

Rx

Bit 3

WDTCtrl

Watch Dog Time

base Control

RW 0

Bit 2

WD2 WD Timer Bit 2 RW 1

Bit 1

WD1 WD Timer Bit 1 RW 1

Bit 0

WD0 WD Timer Bit 0 RW 1

I

2

C Table: M/N Programming & WD Safe Frequency Control Register

Bit 7

M/NEN

PLL1 M/N

Programming

Enable

RW 0

Bit 6

Reserved Reserved RW 0

Bit 5

WD Safe Freq

Source

WD Safe Freq

Source

RW 0

Bit 4

WD SF4 RW 0

Bit 3

WD SF3 RW 0

Bit 2

WD SF2 RW 0

Bit 1

WD SF1 RW 0

Bit 0

WD SF0 RW 0

PWDByte 9 Pin # Name

-

Watch Dog Safe

Freq Programming

bits

-

Type

Name Type

PWD

01PWDByte 8 Pin #

-

Byte Count

Programming b(7:0)

-

Type

-

Byte 10 Pin # Control FunctionName

-

Control Function

01

Disable Enable

01

Normal Alarm

These bits represent X*290ms (or 1.16S)

the watchdog timer waits before it goes to

alarm mode. Default is 7 X 290ms = 2s.

290ms Base 1160ms Base

Writing to this regis ter will configure how

many bytes will be read back, default is

0F = 15 bytes.

Writing to these bit will configure the safe

frequency as Byte0 bit (4:0).

Disable

-

B10b(4:0) Latch Inputs

-

Enable

Normal Alarm

953008BFLF

953008BFLF

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