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CP82C50A-5Z

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
16
FN2958.6
August 19, 2015
82C50A
Programming
The 82C50A is programmed by the control registers LCR,
lER, DLL and DLM, and MCR. These control words define
the character length, number of stop bits, parity, baud rate,
and modem interface.
While the control registers can be written in any order, the
lER should be written to last because it controls the interrupt
enables. Once the 82C50A is programmed and operational,
these registers can be updated any time the 82C50A is not
transmitting or receiving data.
The control signals required to access 82C50A internal
registers are shown below.
Software Reset
A software reset of the 82C50A is a useful method for
returning to a completely known state without a system
reset. Such a reset consists of writing to the LCR, Divisor
Latches, and MCR registers. The LSR and RBR registers
should be read prior to enabling interrupts in order to clear
out any residual data or status bits which may be invalid for
subsequent operation.
Crystal Operation
The 82C50A crystal oscillator circuitry is designed to operate
with a fundamental mode, parallel resonant crystal. Table 8
shows the required crystal parameters and crystal circuit
configuration, respectively.
When using an external clock source, the XTAL1 input is
driven and the XTAL2 output is left open. Power
consumption when using an external clock is typically 50%
of that required when using a crystal. This is due to the
sinusoidal nature of the drive circuitry when using a crystal.
The maximum frequency of the 82C50A is 10MHz with an
external clock or a crystal attached to XTAL1 and XTAL2.
Using the external clock or crystal, and a divide by one
divisor, the maximum BAUDOUT
is 10MHz, and the
maximum data rate is 625Kbps.
TABLE 8. TYPICAL CRYSTAL OSCILLATOR CIRCUIT
PARAMETER
Frequency 1.0 to 10MHz
Type of Operation Parallel Resonant, Fundamental
Mode
Load Capacitance (CL) 20 or 32pF (Typ)
R
SERIES
(Max) 100 (f = 10MHz, CL = 32pF)
200 (f = 10MHz, CL = 20pF)
FIGURE 2. TYPICAL CRYSTAL OSCILLATOR CIRCUIT
CL
XTAL
XTAL1
XTAL2
TO
BAUD RATE
GENERATOR
LOGIC
PIN 17
PIN 16
RS
CL
82C50A
17
FN2958.6
August 19, 2015
82C50A
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to V
CC
+0.5V
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
CX82C50A-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to +70
o
C
IX82C50A-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
JC
(
o
C/W)
Plastic DIP Package. . . . . . . . . . . . . . . 45 N/A
Plastic LCC Package . . . . . . . . . . . . . . 50 N/A
Maximum Junction Temperature
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150
o
C
Max Storage Temperature Range . . . . . . . . . . . . . -65
o
C to +150
o
C
Max Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . .+300
o
C
(Lead Tips Only for Surface Mount Packages)
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1788 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications V
CC
= 5.0V ±10%, T
A
= 0
o
C to +70
o
C (CX82C50A-5) T
A
= -40
o
C to +85
o
C (lX82C50A-5)
SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS
V
IH
Logical One Input Voltage 2.0 - V
V
IL
Logical Zero Input Voltage - 0.8 V
VTH Schmitt Trigger Logic One Input Voltage 2.0 - V MR Input
VTL Schmitt Trigger Logic Zero Input Voltage - 0.8 V MR Input
VIH (CLK) Logical One Clock Voltage V
CC
-0.8 - V External Clock
VlL (CLK) Logical Zero Clock Voltage - 0.8 V External Clock
V
OH
Output High Voltage 3.0 - V I
OH
= -2.5mA
V
CC
-0.4 - V I
OH
= -100A
V
OL
Output Low Voltage - 0.4 V l
OL
= +2.5mA,
II Input Leakage Current -1.0 +1.0 AV
IN
= GND or V
CC
, DIP Pins 9,10,12,
13, 14, 18, 19, 21, 22, 25-28, 35-39
IO Input/Output Leakage Current -10.0 +10.0 AV
O
= GND or V
CC
, DIP Pins 1-8
ICCOP Operating Power Supply Current - 6 mA External Clock F = 2.4576MHz,
V
CC
= 5.5V, V
IN
= V
CC
or GND,
Outputs Open
ICCSB Standby Supply Current - 100 AV
CC
= 5.5V, V
IN
= V
CC
or GND,
Outputs Open
Capacitance T
A
= 25
o
C
SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS
CIN Input Capacitance 15 pF FREQ = 1MHz, all measurements are
referenced to device GND
COUT Output Capacitance 15 pF
CI/O I/O Capacitance 20 pF
18
FN2958.6
August 19, 2015
82C50A
AC Electrical Specifications V
CC
= 5.0V ±10%, T
A
= 0
o
C to +70
o
C (CX82C50A-5) T
A
= -40
o
C to +85
o
C (lX82C50A-5)
Timing Requirements
SYMBOL PARAMETER
82C50A-5
TEST CONDITIONSMIN MAX UNITS
(1) TAW Address Strobe Width 50 - ns
(2) TAS Address Setup Time 60 - ns Note 1
(3) TAH Address Hold Time 0 - ns
(4) TCS Chip Select Setup Time 60 - ns Note 1
(5) TCH Chip Select Hold Time 0 - ns
(6) TDIW DISTR DlSTR
Strobe Width 150 - ns
(7) TRC Read Cycle Delay 270 - ns Note 1
(8) RC Read Cycle = TAR + TDIW + TRC 500 - ns
(9) TDD DISTR DlSTR
to Driver Disable Delay - 75 ns
(10) TDDD Delay From DISTR DlSTR
to Data - 120 ns
(11) THZ DlSTR DISTR to Floating Data Delay 10 75 ns
(12) TDOW DOSTR DOSTR
Strobe Width 150 - ns
(13) TWC Write Cycle Delay 270 - ns Note 1
(14) WC Write Cycle = TAW + TDOW + TWC 500 - ns
(15) TDS Data Setup Time 90 - ns
(16) TDH Data Hold Time 60 - ns
NOTE:
1. “When using the 82C50A in the multiplexed mode (ADS
operational), it will operate in 80C86/88 systems with a maximum 3MHz operating
frequency.”
AC Electrical Specifications V
CC
= 5.0V ±10%, T
A
= 0
o
C to +70
o
C (CX82C50A-5) T
A
= -40
o
C to +85
o
C (lX82C50A-5)
Timing
SYMBOL PARAMETER
82C50A-5
UNITS TEST CONDITIONSMIN MAX
DEMULTIPLEXED OPERATION
(17) TCSC Chip Select Output Delay from Select - 125 ns
(18) TRA Address Hold Time from DISTR DISTR
20 - ns
(19) TRCS Chip Select Hold Time from DISTR DISTR
20 - ns
(20) TAR DISTR DISTR
Delay from Address 80 - ns
(21) TCSR DISTR DISTR
Delay from Chip Select 80 - ns
(22) TWA Address Hold Time from DOSTR DOSTR
20 - ns
(23) TWCS Chip Select Hold Time from DOSTR DOSTR
20 - ns
(24) TAW DOSTR DOSTR
Delay from Address 80 - ns
(25) TCSW DOSTR DOSTR
Delay from Select 80 - ns
(26) TMRW Master Reset Pulse Width 500 - ns
(27) TXH Duration of Clock High Pulse 40 - ns
(28) TXL Duration of Clock Low Pulse 40 ns
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CP82C50A-5Z

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Manufacturer:
Renesas / Intersil
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