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CP82C50A-5Z

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
7
FN2958.6
August 19, 2015
82C50A
Accessible Registers
The three types of internal registers in the 82C50A used in
the operation of the device are control, status, and data
registers. The control registers are the Bit Rate Select
Register DLL and DLM, Line Control Register, Interrupt
Enable Register and the Modem Control registers, while the
status registers are the Line Status Registers and the
Modem Status Register. The data registers are the Receiver
Buffer Register and Transmitter Holding Register. The
Address, Read, and Write inputs are used in conjunction
with the Divisor Latch Access Bit in the Line Control Register
(LCR(7)) to select the register to be written or read (see
Table 1.). Individual bits within these registers are referred to
by the register mnemonic and the bit number in parenthesis.
An example, LCR(7) refers to Line Control Register Bit 7.
The Transmitter Buffer Register and Receiver Buffer
Register are data registers holding from 5-8 data bits. If less
than eight data bits are transmitted, data is right justified to
the LSB. Bit 0 of a data word is always the first serial data bit
received and transmitted. The 82C50A data registers are
double buffered so that read and write operations can be
performed at the same time the UART is performing the
parallel to serial and serial to parallel conversion. This
provides the microprocessor with increased flexibility in its
read and write timing.
TABLE 1. ACCESSING 82C50A INTERNAL REGISTERS
DLAB A2 A1 A0 MNEMONIC REGISTER
0 0 0 0 RBR Receiver Buffer
Register (read only)
0 0 0 0 THR Transmitter Holding
Register (write only)
0 0 0 1 lER Interrupt Enable
Register
X 0 1 0 IIR Interrupt Identification
Register
(read only)
X 0 1 1 LCR Line Control Register
X 1 0 0 MCR Modem Control
Register
X 1 0 1 LSR Line Status Register
X 1 1 0 MSR Modem Status
Register
X 1 1 1 SCR Scratch Register
1 0 0 0 DLL Divisor Latch (LSB)
1 0 0 1 DLM Divisor Latch (MSB)
NOTE: X = “Don’t Care”, 0 = Logic Low, 1 = Logic High
Line Control Register (LCR)
LCR
7
LCR
6
LCR
5
LCR
4
LCR
3
LCR
2
LCR
1
LCR
0
Word
Length
Select
0 0 = 5 Data Bits
0 1 = 6 Data Bits
1 0 = 7 Data Bits
1 1 = 8 Data Bits
Stop
Bit
Select
0 = 1 Stop Bit
1 = 1.5 Stop Bits if 5 Data Bit Word Length is Selected 2 Stop Bits if 6,
7, or 8 Data Bit Word Length is Selected
Parity
Enable
0 = Parity Disabled
1 = Parity Enabled (Generated & Checked)
Even Parity
Select
0 = Odd Parity When Parity is Enabled
1 = Even Parity When Parity is Enabled
Stick Parity 0 = Stick Parity Disabled
1 = When Parity is Enabled Forces the Transmission and Checking of
a Parity Bit of a Known State. Parity Bit Forced to a Logic 1 if LCR
(4) = 0 or to a Logic 0 If LCR (4) = 1.
Break
Control
0 = Break Disabled
1 = Break Enabled. The Serial Output (SOUT) is Forced to the Spacing
(Logic 0) State.
Divisor Latch
Access Bit
0 = Must be Low to Access the Receiver Buffer. Transmitter Holding
Register or the Interrupt Enable Register.
1 = Must be High to Access the Divisor Latches DLL and DLM of the
Baud Rate Generator During a Read or Write Operation.
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FN2958.6
August 19, 2015
82C50A
LINE CONTROL REGISTER (LCR)
The format of the data character is controlled by the Line
Control Register. The contents of the LCR may be read,
eliminating the need for separate storage of the line
characteristics in system memory. The contents of the LCR
are described below.
LCR BITS 0 THRU 7
LCR (0) Word Length Select Bit 0 (WLS0)
LCR (1) Word Length Select Bit 1 (WLS1)
LCR (2) Stop Bit Select (STB)
LCR (3) Parity Enable (PEN)
LCR (4) Even Parity Select (EPS)
LCR (5) Stick Parity
LCR (6) Set Break
LCR (7) Divisor Latch Access Bit (DLAB)
LCR(0) and LCR(1) Word Length Select Bit 0, Word
Length Select Bit 1: The number of bits in each transmitted
or received serial character is programmed as follows:
LCR(2) Stop Bit Select: LCR(2) specifies the number of
stop bits in each transmitted character. If LCR(2) is a logic 0,
one stop bit is generated in the transmitted data. If LCR(2) is
a logic 1 when a 5-bit word length is selected, 1.5 stop bits
are generated. If LCR(2) is a logic 1 when either a 6-, 7-, or
8-bit word length is selected, two stop bits are generated.
The receiver checks for two stop bits if programmed.
LCR(3) Parity Enable: When LCR(3) is high, a parity bit
between the last data word bit and stop bit is generated and
checked.
LCR(4) Even Parity Select: When parity is enabled
(LCR(3) = 1), LCR(4) = 0 selects odd parity, and LCR(4) = 1
selects even parity.
LCR(5) Stick Parity: When parity is enabled (LCR(3) = 1),
LCR(5) = 1 causes the transmission and reception of a parity
bit to be in the opposite state from that indicated by LCR(4).
This allows the user to force parity to a known state and for
the receiver to check the parity bit in a known state.
LCR(6) Break Control: When LCR(6) is set to logic-1, the
serial output (SOUT) is forced to the spacing (logic 0) state.
The break is disabled by setting LCR(6) to a logic-0. The
Break Control bit acts only on SOUT and has no effect on
the transmitter logic. Break Control enables the CPU to alert
a terminal in a computer communications system. If the
following sequence is used, no erroneous or extraneous
characters will be transmitted because of the break.
1. Load an all Os pad character in response to THRE.
2. Set break in response to the next THRE.
3. Wait for the transmitter to be idle, (TEMT = 1), and clear
break when normal transmission has to be restored.
During the break, the transmitter can be used as a character
timer to accurately establish the break duration.
LCR(7) Divisor Latch Access Bit (DLAB): LCR(7) must be
set high (logic 1) to access the Divisor Latches DLL and
DLM of the Baud Rate Generator during a read or write
operation. LCR(7) must be input low to access the Receiver
Buffer, the Transmitter Holding Register, or the Interrupt
Enable Register.
LINE STATUS REGISTER (LSR)
The LSR is a single register that provides status indications.
The LSR is usually the first register read by the CPU to
determine the cause of an interrupt or to poll the status of the
82C50A.
Three error flags OE, FE, and PE provide the status of any
error conditions detected in the receiver circuitry. During
reception of the stop bits, the error flags are set high by an
error condition. The error flags are not reset by the absence
of an error condition in the next received character. The flags
reflect the last character only if no overrun occurred. The
Overrun Error (OE) indicates that a character in the Receiver
Buffer Register has been overwritten by a character from the
Receiver Shift Register before being read by the CPU. The
character is lost. Framing Error (FE) indicates that the last
character received contained incorrect (low) stop bits. This is
caused by the absence of the required stop bit or by a stop
bit too short to be detected. Parity Error (PE) indicates that
the last character received contained a parity error based on
the programmed and calculated parity of the received
character.
The Break Interrupt (BI) status bit indicates that the last
character received was a break character. A break character
is an invalid data character, with the entire character,
including parity and stop bits, logic zero.
The Transmitter Holding Register Empty (THRE) bit
indicates that the THR register is empty and ready to receive
another character. The Transmission Shift Register Empty
(TEMT) bit indicates that the Transmitter Shift Register is
empty, and the 82C50A has completed transmission of the
last character. If the interrupt is enabled (lER(1)), an active
THRE causes an interrupt (INTRPT).
The Data Ready (DR) bit indicates that the RBR has been
loaded with a received character (including Break) and that
the CPU may access this data.
Reading the LSR clears LSR (1) - LSR (4). (OE, PE, FE
and BI).
LCR(1) LCR(0) WORD LENGTH
00 5 Bits
01 6 Bits
10 7 Bits
11 8 Bits
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FN2958.6
August 19, 2015
82C50A
The contents of the Line Status Register are indicated in the
above table and are described below.
LSR(0) Data Ready (DR): Data Ready is set high when an
incoming character has been received and transferred into
the Receiver Buffer Register. LSR(0) is reset low by a CPU
read of the data in the Receiver Buffer Register.
LSR(1) Overrun Error (OE): Overrun Error indicates that
data in the Receiver Buffer Register was not read by the
CPU before the next character was transferred into the
Receiver Buffer Register, overwriting the previous character.
The OE indicator is reset whenever the CPU reads the
contents of the Line Status Register.
LSR(2) Parity Error (PE): Parity Error indicates that the
received data character does not have the correct even or
odd parity, as selected by the Even Parity Select bit (LCR
(4)). The PE bit is set high upon detection of a parity error,
and is reset low when the CPU reads the contents of the
LSR.
LSR(3) Framing Error (FE): Framing Error indicates that
the received character did not have a valid stop bit. LSR(3)
is set high when the stop bit following the last data bit or
parity bit is detected as a zero bit (spacing level). The FE
indicator is reset low when the CPU reads the contents of
the LSR.
LSR(4) Break Interrupt (BI): Break Interrupt is set high
when the received data input is held in the spacing (logic 0)
state for longer than a full word transmission time (start bit +
data bits + parity + stop bits). The B indicator is reset when
the CPU reads the contents of the Line Status Register.
LSR(1) - LSR(4) are the error conditions that produce a
Receiver Line Status interrupt (priority 1 interrupt in the
Interrupt Identification Register (IIR)) when any of the
conditions are detected. This interrupt is enabled by setting
lER (2) = 1 in the Interrupt Enable Register.
LSR(5) Transmitter Holding Register Empty
(THRE): THRE indicates that the 82C50A is ready to accept
a new character for transmission. The THRE bit is set high
when a character is transferred from the Transmitter Holding
Register into the Transmitter Shift Register. LSR(5) is reset
low by the loading of the Transmitter Holding Register by the
CPU. LSR(5) is not reset by a CPU read of the LSR.
When the THRE interrupt is enabled (IER(1) = 1), THRE
causes a priority 3 interrupt in the lIR. If THRE is the interrupt
source indicated in IIR, lNTRPT is cleared by a read of the
IIR.
LSR(6) Transmitter Empty (TEMT): TEMT is set high
when the Transmitter Holding Register (THR) and the
Transmitter Shift Register (TSR) are both empty. LSR(6) is
reset low when a character is loaded into the THR and
remains low until the character is transferred out of SOUT.
TEMT is not reset low by a CPU read of the LSR.
LSR(7): This bit is permanently set to logic 0.
MODEM CONTROL REGISTER (MCR)
The MCR controls the interface with the modem or data set
as described below. The MCR can be written and read. The
RTS
, DTR, OUT1 and OUT2 outputs are directly controlled
by their control bits in this register. A high input asserts a
low (true) at the output pins.
MCR(0): When MCR(0) is set high, the DTR
output is forced
low. When MCR(0) is reset low, the DTR
output is forced
high. The DTR
output of the 82C50A may be input into an
ElA inverting line driver as the 1488 to obtain the proper
polarity input at the modem or data set.
MCR(1): When MCR(1) is set high, the RTS
output is forced
low. When MCR(1) is reset low, the RTS
output is forced
high. The RTS output of the 82C50A may be input into an
ElA inverting line driver as the 1488 to obtain the proper
polarity input at the modem or data set.
MCR(2): When MCR(2) is set high, the OUT1
output is
forced low. When MCR(2) is reset low, the OUT1
output is
forced high. OUT1
is an user designated output.
LSR BITS 0 THRU 7
LOGIC 1 LOGIC 0
LSR (0) Data Ready (DR) Ready Not Ready
LSR (1) Overrun Error (OE) Error No Error
LSR (2) Parity Error (PE) Error No Error
LSR (3) Framing Error (FE) Error No Error
LSR (4) Break Interrupt (BI) Break No Break
LSR (5) Transmitter Holding
Register Empty (THRE)
Empty Not Empty
LSR (6) Transmitter Empty (TEMT) Empty Not Empty
LSR (7) Not Used
MCR BITS 0 THRU 7
MCR BIT
LOGIC 1
MCR BIT
LOGIC 0
MCR (0) Data Terminal Ready
(DTR)
DTR
Output Low
DTR
Output High
MCR (1) Request to Send
(RTS)
RTS
Output Low
RTS
Output High
MCR (2) OUT1 OUT1
Output Low
OUT1
Output High
MCR (3) OUT2 OUT2
Output Low
OUT2
Output High
MCR (4) LOOP LOOP
Enabled
LOOP
Disabled
MCR (5) 0
MCR (6) 0
MCR (7) 0
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CP82C50A-5Z

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