LX1675
PRODUCTION DATA SHEET
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 17
Copyright © 2004
Rev. 1.2a, 2006-02-16
WWW.Microsemi .COM
Multiple Output LoadSHARE™ PWM
TM
®
APPLICATION NOTE CONSIDERATIONS
1. The power N-MOSFET transistor’s total gate charge spec,
(Qg) should not exceed 50nC. This condition will guarantee
operation over the specified ambient temperature range with
600kHz operating frequency. The Qg value of the N-
MOSFET is directly related to the amount of power
dissipation inside the IC package, from the three sets of
MOSFET drivers. The equation relating Qg to the power
dissipation of a MOSFET driver is: Pd = f * Qg * Vd . f =
300KHs and Vd is the supply voltage for the MOSFET
driver. The three bottom MOSFET drivers are powered by
the VCCL pin that is connected to +5V. The upper MOSFET
drivers are connected to a bootstrap supply generated by its
output bridge. The bootstrap supply will ride on top of the
VIN rail. Depending on the thermal environment of the
application circuit, the Qg value of the N-MOSFETs will
have to be less than the 50nC value. A typical configuration
of the input voltage rails to generate the output voltages
required by having the VIN supply on all phases. At the max
Qg value, the three bottom MOSFET drivers will dissipate
75mw each. The upper MOSFET drivers for all three phases
will also operate off of +5volts. Their dissipation is 75mw
each. The total power dissipation for all gate drives is
450mw. Icc x Vcc =15ma x 5 V= 75mW. Total package
power dissipation = 525mW. Using the thermal equation of:
Tj = Ta + Pd * Oja, the Junction temperature for this IC
package is = 23 + .525 * 85 which = 68°C. This means that
the ambient temperature rise has to be less than 82°C. At
600kHz the switching losses double so the ambient
temperature rise has to be less than 44°C.
2.
The Soft-Start reference input has a 100mv threshold, above
which the PWM starts to operate. The internal operating
reference level is set at 800mv. This means that the output
voltage is 12.5% low when the PWM becomes active. This
starts each phase up in the current limit mode without Hiccup
operation. If more than one phase is using the 5V rail for
conversion, then their soft-start capacitor values should be
changed so that the two phases do not start up together. This
will help reduce the amount of 5V input capacitance required.
Also the VCCL pin should have sufficient decoupling
capacitance to keep from drooping back below the UVLO set
point during start up.
3.
It should be noted here that if the VIN power supply voltage
falls between 4.5V to 6.0V the VIN pin and the VCCL pin
should be connected together. If the VIN power supply
voltage is greater than 6V then the two pins are kept separate
and VCCL becomes a 5V output supply for the bootstrap
capacitors. The UVLO is looking for the voltage at the
VCCL pin to be above 4.4V to start up.
4.
When phases 1 and 2 are used in the Bi-phase mode to current
share into the same output load, the phase 2 current is forced to
follow the phase 1 current. It is important to use a larger soft-
start capacitor on phase 2 than phase 1 so that the phase 1
current becomes active before phase 2 becomes active. This
will minimize any start up transient. It is also important to
disable phase 1 and 2 at the same time. Disabling phase 1
without disabling phase 2, in the Bi-phase mode, allows phase
2 turn on and off randomly because it has lost its reference.
5.
The maximum output voltage when using LoadSHARE is
limited by the input common mode voltage of the error
amplifier and cannot exceed the input common mode voltage.
6.
A resistor has been put in series with the gate of the LDO pass
transistor to reduce the output noise level. The resistor value
can be changed to optimize the output transient response versus
output noise.
7.
The LDO controller inside the IC uses the voltage at VSLR pin
as the drive voltage. This pin should be connected to the VIN
voltage to insure reliable operation of the LDO controller. An
additional decoupling capacitor can be connected to this pin to
eliminate any high frequency noise.
8.
The LDO controller has its own soft-start pin so that its turn on
delay can be set so that the voltage rail connected to its pass
transistor has had time to come up first. This will allow a
smooth ramp up of the LDO voltage rail. The voltage rail for
the LDO pass transistor can come from any of the other PWM
phases if desirable.
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